LAPIS Semiconductor ML610421, User Manual, Page: 177 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 13 Watchdog Timer
12 – 5
12.3 Description of Operation
The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start..
Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when
WDP is "1".
WDP is reset to “0” at the time of system reset or when the WDT counter overflows and is inverted whenever data is
written to WDTCON.
When the WDT counter cannot be cleared within the WDT counter overflow period (T
WOV
), a watchdog timer interrupt
(WDTINT) occurs. If the WDT counter is not cleared even by the software processing performed following the
watchdog timer interrupt and overflow occurs again, WDT reset occurs and the mode shifts to a system reset mode.
For the overflow period (TWOV) of the WDT counter, one of 125ms, 500ms, 2s, and 8s can be selected by the
watchdog mode register (WDTMOD).
Clear the WDT counter within the clear period of the WDT counter shown in Table 12-1.
Table 12-1 Clear Period of WDT Counter
WDT1 WDT0 T
WOV
T
WCL
0 0 125 ms Approx. 121 ms
0 1 500 ms Approx. 496 ms
1 0 2000 ms Approx. 1996 ms
1 1 8000 ms Approx. 7996 ms