LAPIS Semiconductor ML610421, User Manual, Page: 117 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 7 Time Base Counter
7 – 7
7.3 Description of Operation
7.3.1 Low-Speed Time Base Counter
The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset.
The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as time base interrupts and an interrupt is
requested on the falling edge of each output. Each of LTBC outputs is also used as an operation clock for peripheral
circuits.
The output data of T128HZ to T1HZ of LTBC can be read from the low-speed time base counter register (LTBR).
When reading the data, read LTBR twice and check that the two values coincide to prevent reading of undefined data
during counting.
Figure 7-3 shows an example of program to read LTBR.
LEA offset LTBR ; EA
←
LTBR address
MARK:
L R0, [EA] ; 1st read
L R1, [EA] ; 2nd read
;
CMP R0, R1 ; Comparison for LTBR
BNE MARK ; To MARK when the values do not coincide
;
:
Figure 7-3 Programming Example for Reading LTBR
LTBR is reset when write operation is performed and the T128HZ to T1HZ outputs are set to “0”. Write data is invalid.
Since an interrupt occurs if a falling edge occurs in the T128Hz to T1Hz outputs during writing to LTBR, take care in
software programming.
Figure 7-4 shows interrupt generation timing and reset timing of the time base counter output by writing to LTBR.
Figure 7-4 Interrupt Timing and Reset Timing by Writing to LTBR
LTBR Write
T1HZ
T2HZ
T4HZ
T8HZ
T16HZ
T32HZ
T64HZ
T128HZ
T256HZ
T16HZ
Indicates interrupt timing