LAPIS Semiconductor ML610421, User Manual, Page: 96 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 3
6.2.2 Frequency Control Register 0 (FCON0)
Address: 0F002H
Access: R/W
Access size: 8/16 bits
Initial value: 33H
7 6 5 4 3 2 1 0
FCON0
 
OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 1 0 0 1 1
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
•
SYSC1, SYSC0 (bits 1, 0)
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system clock
and periphera1 circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK
can be selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of this LSI is 4.2
MHz.
At system reset, 1/8OSCLK is selected.
SYSC1 SYSC0 Description
0 0
OSCLK (1/2OSCLK in built-in PLL oscillation mode)
0 1 1/2OSCLK
1 0
1/4OSCLK
1 1 1/8OSCLK (initial value)
•
OSCM1, OSCM0 (bits 3, 2)
The OSCM1 and OSCM0 bits are used to select the mode of the high-speed clock generation circuit. RC oscillation
mode, crystal/ceramic oscillation mode, PLL oscillation mode, or external clock input mode can be selected.
The setting of OSCM1 and OSCM0 can be changed only when high-speed oscillation is being stopped (ENOSC bit
of FCON1 is “0”).
At system reset, RC oscillation mode is selected.
−
When switching the high-speed oscillation mode, please first switch back to low speed clock before switching to
other high-speed clock (set the ENOSC bit and SYSCLK bit of FCON1 to “0”).
OSCM1 OSCM0 Description
0 0 RC oscillation mode (initial value)
0 1 Crystal/ceramic oscillation mode
1 0 Built-in PLL oscillation mode
1 1 External clock input mode
•
OUTC1, OUTC0 (bits 5, 4)
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output when
the secondary function of the port is used.
OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
OUTC1 OUTC0 Description
0 0 OSCLK
0 1 1/2OSCLK
1 0 1/4OSCLK
1 1 1/8OSCLK (initial value)