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ML610Q421/ML610Q422/ML610421 User’s Manual 

Chapter 14    UART 

 

14 – 10 

•

 

U0FUL

 (bit 3) 

The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. 
When transmit  data  is  written in UA0BUF in transmit mode, this bit is set to “1” and when transmit  data is 
transferred to the shift register, this bit is set to “0”.    To transmit data consecutively, write the next transmit data to 
UA0BUF after checking that the U0FUL flag has been set to “0”. 
The U0FUL bit is fixed to “0” in receive mode. 
 

U0FUL 

Description 

0 

There is no data in the transmit/receive buffer. (Initial value) 

1 

There is data in the transmit/receive buffer. 

 

Summary of Contents for ML610421

Page 1: ...ML610Q421 ML610Q422 ML610421 User s Manual Issue Date Feb 9 2015 FEUL610Q421 06...

Page 2: ...tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation equi...

Page 3: ...cations of the assembler language CCU8 User s Manual Description on the method of operating the compiler CCU8 Programming Guide Description on the method of programming CCU8 Language Reference Descrip...

Page 4: ...high voltage signal levels VIH and VOH as specified by the electrical characteristics L level 0 level Indicates low voltage signal levels VIL and VOL as specified by the electrical characteristics Re...

Page 5: ...7 Pad Coordinates of ML610Q422 Chip 1 14 1 3 1 8 Pad Coordinates of ML610421 Chip 1 15 1 3 2 List of Pins 1 16 1 3 2 1 List of ML610Q421 ML610Q422 Pins 1 16 1 3 2 2 List of ML610421 Pins 1 20 1 3 3 D...

Page 6: ...5 1 5 1 1 Features 5 1 5 2 Description of Registers 5 2 5 2 1 List of Registers 5 2 5 2 2 Interrupt Enable Register 1 IE1 5 3 5 2 3 Interrupt Enable Register 2 IE2 5 4 5 2 4 Interrupt Enable Register...

Page 7: ...7 7 Time Base Counter 7 1 7 1 Overview 7 1 7 1 1 Features 7 1 7 1 2 Configuration 7 1 7 2 Description of Registers 7 3 7 2 1 List of Registers 7 3 7 2 2 Low Speed Time Base Counter LTBR 7 4 7 2 3 Hig...

Page 8: ...trol Register 0 TM3CON0 10 15 10 2 14 Timer 0 Control Register 1 TM0CON1 10 16 10 2 15 Timer 1 Control Register 1 TM1CON1 10 17 10 2 16 Timer 2 Control Register 1 TM2CON1 10 18 10 2 17 Timer 3 Control...

Page 9: ...isters 13 11 13 4 1 Functioning P42 SOUT0 P41 SCK0 and P40 SIN0 as the SSIO Master mode 13 11 13 4 2 Functioning P42 SOUT0 P41 SCK0 and P40 SIN0 as the SSIO Slave mode 13 12 13 4 3 Functioning P46 SOU...

Page 10: ...te 15 9 15 3 1 7 Stop Condition 15 10 15 3 2 Communication Operation Timing 15 11 15 3 3 Operation Waveforms 15 13 15 4 Specifying port registers 15 14 15 4 1 Functioning P41 SCL and P40 SDA as the I2...

Page 11: ...isters 0 1 P2CON0 P2CON1 19 4 19 2 4 Port 2 Mode Register P2MOD 19 5 19 3 Description of Operation 19 6 19 3 1 Output Port Function 19 6 19 3 2 Secondary Function 19 6 Chapter 20 20 Port 3 20 1 20 1 O...

Page 12: ...st of Pins 23 1 23 2 Description of Registers 23 2 23 2 1 List of Registers 23 2 23 2 2 Melody 0 Control Register MD0CON 23 3 23 2 3 Melody 0 Tempo Code Register MD0TMP 23 4 23 2 4 Melody 0 Scale Code...

Page 13: ...25 9 25 3 1 Settings of A D Conversion Channels 25 9 25 3 2 Operation of the Successive Approximation A D Converter 25 10 Chapter 26 26 LCD Drivers 26 1 26 1 Overview 26 1 26 1 1 Features 26 3 26 1 2...

Page 14: ...tery Level Detector 27 6 Chapter 28 28 Power Supply Circuit 28 1 28 1 Overview 28 1 28 1 1 Features 28 1 28 1 2 Configuration 28 1 28 1 3 List of Pins 28 1 28 2 Description of Operation 28 2 Chapter 2...

Page 15: ...Chapter 1 Overview...

Page 16: ...pulations bit logic operations jump conditional jump call return stack manipulations arithmetic shift and so on On Chip debug function ML610Q421 ML610Q422 only Minimum instruction execution time 30 5...

Page 17: ...Fast mode 400 kbps MH standard mode 100 kbps 1MH 50kbps 500kHz Melody driver Scale 29 types Melody sound frequency 508 Hz to 32 768 kHz Tone length 63 types Tempo 15 types Buzzer output mode 4 output...

Page 18: ...es One of 16 levels Judgment accuracy 2 Typ Clock Low speed clock This LSI can not guarantee the operation withoug low speed clock Crystal oscillation 32 768 kHz High speed clock Built in RC oscillati...

Page 19: ...L610422 xxxWA Mask ROM 20 C to 70 C ML610421P xxxWA Mask ROM 40 C to 85 C ML610422P xxxWA Mask ROM 40 C to 85 C 120 pin plastic TQFP ROM type Operating temperature Product availability ML610Q421 xxxTB...

Page 20: ...BUS Controller Instruction Register TBC INT 4 INT 1 INT 1 INT 1 WDT INT 4 8bit Timer 4 Capture 2 INT 1 PWM GPIO P00 to P03 P10 to P11 P20 to P22 INT 5 NMI P30 to P35 P40 to P47 PA0 to PA7 Data bus PW...

Page 21: ...er Instruction Register TBC INT 4 INT 1 INT 1 INT 1 WDT INT 4 8bit Timer 4 Capture 2 INT 1 PWM GPIO P00 to P03 P10 to P11 P20 to P22 INT 5 NMI P30 to P35 P40 to P47 Data bus PWM0 Melody INT 1 MD0 TEST...

Page 22: ...r TBC INT 4 INT 1 INT 1 INT 1 WDT INT 4 8bit Timer 4 Capture 2 INT 1 PWM GPIO P00 to P03 P10 to P11 P20 to P22 INT 5 NMI P30 to P35 P40 to P47 PA0 to PA7 Data bus PWM0 Melody INT 1 MD0 TEST RESET_N OS...

Page 23: ...C3 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG18 SEG17 SEG16 SEG15 SEG14 RESET_N P42 P43 P44 P45 P46 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 VL1 VL3 VL2 NMI VSS XT1 VL4 C1 C2 P47 VPP NC SEG...

Page 24: ...1 VL3 VL2 NMI VSS XT1 VL4 C1 C2 P47 VPP 1 NC SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG48 SEG47 SEG46 SEG45...

Page 25: ...46 SEG6 PA4 102 45 SEG5 PA5 103 44 SEG4 PA6 104 43 SEG3 PA7 105 42 SEG2 P20 LED0 106 P21 LED1 107 P22 LED2 108 P40 SDA 109 P41 SCL 110 Vss 111 AVSS 112 VREF 113 AIN0 114 AIN1 115 AVDD 116 1 2 3 4 5 6...

Page 26: ...46 SEG6 COM12 102 45 SEG5 COM13 103 44 SEG4 COM14 104 43 SEG3 COM15 105 42 SEG2 P20 LED0 106 P21 LED1 107 P22 LED2 108 P40 SDA 109 P41 SCL 110 Vss 111 AVSS 112 VREF 113 AIN0 114 AIN1 115 AVDD 116 1 2...

Page 27: ...Layout of ML610421 Chip Note The assignment of the pads P30 to P35 are not in order Chip size 2 80 mm 2 86mm PAD count 115 pins Minimum PAD pitch 80 m PAD aperture 70 m 70 m Chip thickness 350 m Volt...

Page 28: ...16 VDD 40 1404 66 SEG26 600 1404 116 AVDD 1384 1172 17 VDDL 40 1404 67 SEG27 520 1404 18 Vss 120 1404 68 SEG28 440 1404 19 VDDX 200 1404 69 SEG29 360 1404 20 XT0 360 1404 70 SEG30 280 1404 21 XT1 520...

Page 29: ...092 16 VDD 40 1404 66 SEG26 600 1404 116 AVDD 1384 1172 17 VDDL 40 1404 67 SEG27 520 1404 18 Vss 120 1404 68 SEG28 440 1404 19 VDDX 200 1404 69 SEG29 360 1404 20 XT0 360 1404 70 SEG30 280 1404 21 XT1...

Page 30: ...294 1162 16 VDDL 110 1324 66 SEG27 520 1324 17 Vss 190 1324 67 SEG28 440 1324 18 VDDX 270 1324 68 SEG29 360 1324 19 XT0 350 1324 69 SEG30 280 1324 20 XT1 510 1324 70 SEG31 200 1324 21 Vss 590 1324 71...

Page 31: ...tion type ADC 116 116 AVDD Positive power supply pin for successive approximation type ADC 24 24 VL1 Power supply pin for LCD bias internally generated 25 25 VL2 Power supply pin for LCD bias internal...

Page 32: ...pacitor connection pin 11 11 P34 I O Input output port RCT0 O RC type ADC0 resistor capacitor sensor connection pin PWM0 O PWM output 12 12 P32 I O Input output port RS0 O RC type ADC0 reference resis...

Page 33: ...O LCD common pin 102 COM12 O LCD common pin 103 COM13 O LCD common pin 104 COM14 O LCD common pin 105 COM15 O LCD common pin 40 40 SEG0 O LCD segment pin 41 41 SEG1 O LCD segment pin 42 42 SEG2 O LCD...

Page 34: ...nt pin 72 72 SEG32 O LCD segment pin 73 73 SEG33 O LCD segment pin 74 74 SEG34 O LCD segment pin 75 75 SEG35 O LCD segment pin 76 76 SEG36 O LCD segment pin 77 77 SEG37 O LCD segment pin 78 78 SEG38 O...

Page 35: ...type ADC 23 VL1 Power supply pin for LCD bias internally generated 24 VL2 Power supply pin for LCD bias internally generated 25 VL3 Power supply pin for LCD bias internally generated 26 VL4 Power sup...

Page 36: ...output port RCT0 O RC type ADC0 resistor capacitor sensor connection pin PWM0 O PWM output 11 P32 I O Input output port RS0 O RC type ADC0 reference resistor connection pin 12 P33 I O Input output por...

Page 37: ...n COM8 O LCD common pin COM9 O LCD common pin COM10 O LCD common pin COM11 O LCD common pin COM12 O LCD common pin COM13 O LCD common pin COM14 O LCD common pin COM15 O LCD common pin 39 SEG0 O LCD se...

Page 38: ...SEG30 O LCD segment pin 70 SEG31 O LCD segment pin 71 SEG32 O LCD segment pin 72 SEG33 O LCD segment pin 73 SEG34 O LCD segment pin 74 SEG35 O LCD segment pin 75 SEG36 O LCD segment pin 76 SEG37 O LCD...

Page 39: ...0 pin Secondary OUTCLK O High speed clock output pin This pin is used as the secondary function of the P21 pin Secondary General purpose input port P00 P03 I General purpose input port Since these pin...

Page 40: ...itive PWM PWM0 O PWM0 output pin This pin is used as the tertiary function of the P43 or P34 pin Tertiary Positive T02P0CK O PWM0 external clock input pin This pin is used as the primary function of t...

Page 41: ...nction of the P46 pin Secondary RT1 O Resistor sensor connection pin for measurement of Channel 1 This pin is used as the secondary function of the P47 pin Secondary Successive approximation type A D...

Page 42: ...ors CL0 and CL1 see measuring circuit 1 are connected between this pin and VSS VDDX Plus side power supply pin internally generated for low speed oscillation Capacitor Cx see measuring circuit 1 is co...

Page 43: ...ET_N Open TEST Open NMI Open P00 to P03 VDD or VSS P10 to P11 VDD P20 to P22 Open P30 to P35 Open P40 to P47 Open PA0 to PA7 2 Open COM0 to 7 Open COM8 to 15 3 Open SEG0 to 49 Open 1 ML610Q421 ML610Q4...

Page 44: ...Chapter 2 CPU and Memory Space...

Page 45: ...space consists of 1 segments and has 32 Kbyte 16 Kword capacity Figure 2 1 shows the configuration of the program memory space CSR PC Segment0 0 0000H Vector Table Area or Program Code ROM Window Are...

Page 46: ...Data address Segment 0 DSR Data address Segment 8 0 0000H ROM Window Area 8 0000H ROM Reference Area 0 7DFFH 8 7DFFH 0 7E00H Unused Area 8 7E00H Test Data Area 8 7FFFH 8 8000H Unused Area 0 0DFFFH 0 0...

Page 47: ...22 ML610421 User s Manual Chapter 2 CPU and Memory Space 2 3 2 6 Description of Registers 2 6 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F000H Data segment regist...

Page 48: ...R W R W R W R W Initial value 0 0 0 0 0 0 0 0 DSR is a special function register SFR to retain a data segment For details of DSR see nX U8 100 Core Instruction Manual Description of Bits DSR3 DSR0 bi...

Page 49: ...Chapter 3 Reset Function...

Page 50: ...l pull up resistor The low speeed oscillation stop deteciton time is 3 ms typ 250 ms 1 sec 4 sec or 16 sec can be selected as the 2nd watchdog timer WDT overflow period Built in reset status register...

Page 51: ...alize the contents of RSTAT to 00H Description of Bits POR bit 0 The POR bit is a flag that indicates that the power on reset is generated This bit is set to 1 when powered on POR Description 0 Power...

Page 52: ...zed However the initialization is not performed by software reset due to execution of the BRK instruction See Appendix A Registers for the initial values of the SFRs 3 CPU is initialized All the regis...

Page 53: ...Chapter 4 MCU Control Function...

Page 54: ...reducing the current consumption 4 1 1 Features HALT mode where the CPU stops operating and only the peripheral circuit is operating STOP mode where both low speed oscillation and high speed oscillat...

Page 55: ...Word R W Size Initial value 0F008H Stop code acceptor STPACP W 8 0F009H Standby control register SBYCON W 8 00H 0F028H Block control register 0 BLKCON0 R W 8 00H 0F029H Block control register 1 BLKCO...

Page 56: ...o 1 in this state the mode is changed to the STOP mode When the STOP mode is set the STOP code acceptor is disabled When another instruction is executed between the instruction that writes 5nH to STPA...

Page 57: ...s used for setting a HALT mode When the HALT bit is set to 1 the mode is changed to the HALT mode When the NMI interrupt request WDT interrupt request or enabled the interrupt enable flag is 1 interru...

Page 58: ...ng Timer 2 initial value 1 Disable operating Timer 2 DTM1 bit 1 The DTM1 bit is used to control Timer1 operation When the DTM1 bit is set to 1 the circuits related to Timer 1 are reset and turned off...

Page 59: ...lated to 1kHz Timer are reset and turned off DT1K Description 0 Enable operating 1kHz Timer initial value 1 Disable operating 1kHz Timer DPW0 bit 0 The DPW0 bit is used to control PWM0 operation When...

Page 60: ...to UART are reset and turned off DUA0 Description 0 Enable operating UART initial value 1 Disable operating UART DSIO0 bit 0 The DSIO0 bit is used to control SSIO operation When the DSIO0 bit is set...

Page 61: ...DMD0 bit is set to 1 the circuits related to Melody Buzzer are reset and turned off DMD0 Description 0 Enable operating Melody Buzzer initial value 1 Disable operating Melody Buzzer Note When certain...

Page 62: ...operation When the DBLD bit is set to 1 the circuits related to BLD are reset and turned off DBLD Description 0 Enable operating BLD initial value 1 Disable operating BLD driver DXTSP bit 4 The DXTSP...

Page 63: ...eripherals stop Writing to every SFR special function register in the corresponding peripherals is not valid while the bits of block control registers are set to 1 and returns the initial value for re...

Page 64: ...t are set in the addresses 0002H and 0003H For details of the BRK instruction and PSW see the nX U8 100 Core Instruction Manual and for the reset function see Chapter 3 Reset Function 4 3 2 HALT Mode...

Page 65: ...bit is set to 0 and low speed oscillation restarts If the high speed clock was oscillating before the STOP mode is entered the high speed oscillation restarts When the high speed clock was not oscilla...

Page 66: ...e of the low speed oscillation start time TXTL and low speed clock LSCLK oscillation settling time 8192 count For the high speed oscillation start time TXTH and low speed oscillation start time TXTL s...

Page 67: ...instruction that sets the STP HLT bit to 1 then goes to the interrupt routine Table 4 2 Return Operation from STOP HALT Mode Maskable Interrupt ELEVEL MIE IEn m IRQn m Return operation from STOP HALT...

Page 68: ...nitial value for read Ensure the bits are reset to 0 before using the peripherals to enable the operation BLKCON0 register controls disables enables operation of Timer 0 Timer 1 Timer 2 and Timer 3 BL...

Page 69: ...Chapter 5 Interrupts INTs...

Page 70: ...hapter 12 Watchdog Timer Chapter 13 Synchronous Serial Port Chapter 14 UART Chapter 15 I2 C Bus Interface Chapter 16 NMI Chapter 17 Port0 Chapter 18 Port1 Chapter 19 Port2 Chapter 20 Port3 Chapter 23...

Page 71: ...IE4 R W 8 00H 0F015H Interrupt enable register 5 IE5 R W 8 00H 0F016H Interrupt enable register 6 IE6 R W 8 00H 0F017H Interrupt enable register 7 IE7 R W 8 00H 0F018H Interrupt request register 0 IRQ...

Page 72: ...t enable flag MIE is set to 0 but the corresponding flag of IE1 is not reset Description of Bits EP00 bit 0 EP00 is the enable flag for the input port P00 pin interrupt P00INT EP00 Description 0 Disab...

Page 73: ...When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE2 is not reset Description of Bits ESIO0 bit 0 ESIO0 is the enable flag for the synchrono...

Page 74: ...is a special function register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE3...

Page 75: ...interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE4 is not reset Description of Bits EUA0 bit 0 EUA0 is the enable flag f...

Page 76: ...E5 is a special function register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of...

Page 77: ...rupt enable flag MIE is set to 0 but the corresponding flag of IE6 is not reset Description of Bits EPW0 bit 0 EPW0 is the enable flag for the PWM0 interrupt PW0INT EPW0 Description 0 Disabled initial...

Page 78: ...nction register SFR to control enable disable for each interrupt request When an interrupt is accepted the master interrupt enable flag MIE is set to 0 but the corresponding flag of IE7 is not reset D...

Page 79: ...f the Mask Interrupt Enable flag MIE Each IRQ0 request flag is set to 1 regardless of the MIE value when an interrupt is generated By setting the IRQ0 request flag to 1 by software an interrupt can be...

Page 80: ...n interrupt can be generated The corresponding flag of IRQ1 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QP00 bit 0 QP00 is the request flag for the in...

Page 81: ...y setting the IRQ2 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ2 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of B...

Page 82: ...upt enable register IE3 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ3 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ3...

Page 83: ...MIE is set to 1 By setting the IRQ4 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ4 is set to 0 by hardware when the interrupt request is accepted by the CP...

Page 84: ...upt enable register IE5 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ5 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ5...

Page 85: ...an interrupt can be generated The corresponding flag of IRQ6 is set to 0 by hardware when the interrupt request is accepted by the CPU Description of Bits QPW0 bit 0 QPW0 is the request flag for the...

Page 86: ...r IE7 is set to 1 and the master interrupt enable flag MIE is set to 1 By setting the IRQ7 request flag to 1 by software an interrupt can be generated The corresponding flag of IRQ7 is set to 0 by har...

Page 87: ...NMINT 000AH 3 P00 interrupt P00INT 0010H 4 P01 interrupt P01INT 0012H 5 P02 interrupt P02INT 0014H 6 P03 interrupt P03INT 0016H 7 Synchronous serial port 0 interrupt SIO0INT 0020H 8 Successive approxi...

Page 88: ...ocessing of program shifts to the interrupt destination 1 Transfer PC to ELR2 2 Transfer CSR to ECSR2 3 Transfer PSW to EPSW2 4 Set the ELEVEL field to 2 5 Load the interrupt start address into PC 5 3...

Page 89: ...e end of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW A 1 2 When multiple interrupts are enabled P...

Page 90: ...ltiple interrupts are enabled Processing immediately after the start of interrupt routine execution Specify PUSH LR ELR EPSW to save the interrupt return address the subroutine return address and the...

Page 91: ...nd PSW B 2 2 When a subroutine is called by the program in executing an interrupt routine Processing immediately after the start of interrupt routine execution Specify PUSH LR ELR EPSW to save the int...

Page 92: ...ion at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section an interrupt is generated immediately following the execution of the instruction at the beginn...

Page 93: ...Chapter 6 Clock Generation Circuit...

Page 94: ...clock Software selection 500 kHz RC oscillation mode Crytal ceramic oscillation mode Built in PLL oscillation mode External clock input mode 6 1 2 Configuration Figure 6 1 shows the configuration of t...

Page 95: ...onnecting a crystal ceramic resonator for high speed clock Used for the secondary function of the P10 pin P11 OSC1 O Pin for connecting a crystal ceramic resonator for high speed clock Used for the se...

Page 96: ...LK 1 1 1 8OSCLK initial value OSCM1 OSCM0 bits 3 2 The OSCM1 and OSCM0 bits are used to select the mode of the high speed clock generation circuit RC oscillation mode crystal ceramic oscillation mode...

Page 97: ...of FCON1 to 0 The oscillators that are connected to the P10 OSC0 and P11 OSC1 pins must not exceed 4 2 MHz In external clock mode input a clock that does not exceed 4 2 MHz When a built in PLL oscilla...

Page 98: ...ted for system clock SYSCLK Description 0 LSCLK 1 HSCLK initial value ENOSC bit 1 The ENOSC bit is used to select enable disable of the oscillation of the high speed clock oscillator ENOSC Description...

Page 99: ...illation and the XT0 and XT1 pins become Hiz Hi Impedance state When the ENMLT bit of FCON1 is set to 1 the 2 low speed clock circuit starts to generate the LSCLK 2 64kHz Figure 6 2 Circuit Configurat...

Page 100: ...n start time TXTL see Appendix C Electrical Characteristics Figure 6 3 Operation of Low Speed Clock Generation Circuit Note After the power supply is turned on CPU starts operation with a high speed c...

Page 101: ...is started when RC oscillation clock pulse count reaches 128 after oscillation is enabled ENOSC is set to 1 In 500 kHz RC oscillation mode both the P10 OSC0 pin and the P11 OSC1 pin can be used as gen...

Page 102: ...e crystal ceramic oscillation mode can be used within a VDD range of 1 8 V to 3 6 V Select a frequency according to the operating voltage range by using the power supply voltage detection circuit BLD...

Page 103: ...lation 32 768kHz is necessary The frequency of 32 768kHz is not adjusted by the frequency adjustment circuit of the time base counter 6 3 2 4 External Clock Input Mode In external clock input mode ext...

Page 104: ...ation can be started by setting the ENOSC bit to 1 after selecting a high speed oscillation mode in FCON0 and a high speed oscillation frequency After the start of oscillation HSCLK starts supply of a...

Page 105: ...n waveform High speed clock HSCLK High speed oscillation enable ENOSC High speed oscillation Count 4096 Start of high speed oscillation STOP mode Generation of external interrupt High speed oscillatio...

Page 106: ...g Processing HSCLK LSCLK Note After the power is turned on or if the system clock is switched from HSCLK to LSCLK immediately following return from the STOP mode the CPU becomes inactive until LSCLK s...

Page 107: ...RC oscillation mode or low speed clock LSCLK As necessary check VDD 1 3V or higher for using the 500kHz RC oscillation clock VDD 1 8V TWAIT 500 s 500 kHz RC oscillation mode TWAIT 20 ms Crystal ceram...

Page 108: ...MD Data 1 Set P21C1 bit bit1 of P2CON1 register to 1 and set P21C0 bit bit1 of P2CON0 register to 1 for specifying the P21 as CMOS output Reg name P2CON1 register Address 0F213H Bit 7 6 5 4 3 2 1 0 Bi...

Page 109: ...specifying P20 as CMOS output Reg name P2CON1 register Address 0F213H Bit 7 6 5 4 3 2 1 0 Bit name P22C1 P21C1 P20C1 Data 1 Reg name P2CON0 register Address 0F212H Bit 7 6 5 4 3 2 1 0 Bit name P22C0 P...

Page 110: ...Chapter 7 Time Base Counter...

Page 111: ...pm Adjustment accuracy Approx 0 48ppm by using the low speed time base counter frequency adjustment registers LTBADJH and LTBADJL HTBC generates HTB1 to HTB32 signals by dividing the high speed clock...

Page 112: ...r frequency divide register Figure 7 2 Configuration of High Speed Time Base Counter Note The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of Frequency control reg...

Page 113: ...Symbol Word R W Size Initial value 0F00AH Low speed time base counter register LTBR R W 8 00H 0F00BH High speed time base counter frequency divide register HTBDR R W 8 00H 0F00CH Low speed time base...

Page 114: ...W R W R W Initial value 0 0 0 0 0 0 0 0 LTBR is a special function register SFR to read the T128HZ T1HZ outputs of the low speed time base counter The T128HZ T1HZ outputs are set to 0 when write oper...

Page 115: ...HTD3 HTD0 bits are used to set the frequency divide ratio of the 4 bit 1 n counter The frequency divide ratios selectable include 1 1 to 1 16 HTD3 HTD2 HTD1 HTD0 Description Divide ratio Frequency of...

Page 116: ...e 00H 7 6 5 4 3 2 1 0 LTBADJH LADJS LADJ9 LADJ8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 LTBADJL and LTBADJH are special function registers SFRs to set the frequency adjustmen...

Page 117: ...lues coincide to prevent reading of undefined data during counting Figure 7 3 shows an example of program to read LTBR LEA offset LTBR EA LTBR address MARK L R0 EA 1st read L R1 EA 2nd read CMP R0 R1...

Page 118: ...unter the divided clock 1 16 HSCLK to 1 1 HSCLK selected by the high speed time base counter divide register HTBDR is generated as HTBCLK HTBCLK is used as a timer and also as an operation clock of PW...

Page 119: ...0 0 0 1 001H 0 48 0 0 0 0 0 0 0 0 0 0 0 000H 0 1 1 1 1 1 1 1 1 1 1 1 7FFH 0 48 1 1 1 1 1 1 1 1 1 1 0 7FEH 0 95 1 0 0 0 0 0 0 0 0 0 1 401H 487 80 1 0 0 0 0 0 0 0 0 0 0 400H 488 28 The adjustment value...

Page 120: ...37C used for 16bit timer 2 3 frequency measurement mode is generated in the time base conter block See Chapter 10 Timer for more detail about the frequency measurement function Figure 7 6 437c signal...

Page 121: ...Chapter 8 Capture...

Page 122: ...1 Features Time base capture 2ch 4096Hz to 32Hz 8 1 2 Configuration Figure 8 1 shows the configuration of the capture circuit CAPCON Capture control register CAPSTAT Capture status register CAPR0 Capt...

Page 123: ...egisters 8 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F090H Capture control register CAPCON R W 8 00H 0F091H Capture status register CAPSTAT R W 8 00H 0F092H Ca...

Page 124: ...0 0 0 0 0 0 CAPCON is a special function register SFR to control the capture circuit Description of Bits ECAP0 bit 0 The ECAP0 bit is used to start or stop the operation of capture 0 ECAP0 Description...

Page 125: ...that data is captured in capture data register 0 CAPR0 When the CAPF0 bit is set to 1 the next capture operation is stopped So perform the write operation to capture data register 0 CAPR0 to clear th...

Page 126: ...P00 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CAPR0 is a register in which capture data is stored The T4KHZ to T32HZ signals of the low speed time base counter LTBC are capture...

Page 127: ...P10 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CAPR1 is a register in which capture data is stored The T4KHZ to T32HZ signals of the low speed time base counter LTBC are capture...

Page 128: ...f the capture status register CAPSTAT is set to 1 When the capture flag CAPF0 CAPF1 is 1 the following capture operation stops After reading the value captured in the capture register 0 or 1 CAPR0 CAP...

Page 129: ...Chapter 9 1 kHz Timer 1kHzTM...

Page 130: ...counter basis represented by a decimal number can be obtained easily The timer can be applied to period measurement for stopwatches For the timer base counter see Chapter 7 Time Base Counter 9 1 1 Fea...

Page 131: ...Description of Registers 9 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F080H 1 kHz timer count register L T1KCRL T1KCR R W 8 16 00H 0F081H 1 kHz timer count reg...

Page 132: ...ss R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 T1KCRH T1KC11 T1K010 T1KC9 T1KC8 T1KC7 T1K06 T1KC5 T1KC4 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 T1KCRL and T1KCRH...

Page 133: ...T1KCON is a special function register SFR to control the 1 kHz timer Description of Bits T1KRUN bit 0 The T1KRUN bit is used to control start stop of the count operation of the 1 kHz timer counter T1K...

Page 134: ...interrupt can be selected between the 10Hz interrupt or 1Hz interrupt using the T1KSEL bit of T1KCON When write operation is performed for T1KCRL or T1KCRH the value of the binary ternary counter and...

Page 135: ...Chapter 10 Timers...

Page 136: ...nt mode which can count HTBCLK and generates the timer interrupt TM3INT when the count ends Using the count data to know the frequency by software can determine more accurate baud rate 10 1 2 Configur...

Page 137: ...3 Figure 10 1 Configuration of Timers TM2C Data bus TM3NT LSCLK TM2CON0 TM2CON1 R HTBCLK Write TM3C T2CK Write TM2C 8 8 TM3C R 8 External clock P44 T02P0CK P45 T13P1CK TM3C latch Read TM2C Counter 16...

Page 138: ...ter TM1D TM1DC R W 8 16 0FFH 0F035H Timer 1 counter register TM1C R W 8 00H 0F036H Timer 1 control register 0 TM1CON0 TM1CON R W 8 16 00H 0F037H Timer 1 control register 1 TM1CON1 R W 8 00H 0F038H Tim...

Page 139: ...6 5 4 3 2 1 0 TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM0D is a special function register SFR to set the value to be compared wi...

Page 140: ...4 3 2 1 0 TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM1D is a special function register SFR to set the value to be compared with t...

Page 141: ...4 3 2 1 0 TM2D T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM2D is a special function register SFR to set the value to be compared with t...

Page 142: ...4 3 2 1 0 TM3D T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 TM3D is a special function register SFR to set the value to be compared with t...

Page 143: ...formed to either the low order TM0C or high order TM1C both the low order and the high order are set to 0000H During timer operation the contents of TM0C may not be read depending on the conditions of...

Page 144: ...er and the high order are set to 0000H When reading TM1C in 16 bit timer mode be sure to read TM0C first since the count value of TM1C is stored in the TM1C latch when TM0C is read During timer operat...

Page 145: ...formed to either the low order TM2C or high order TM3C both the low order and the high order are set to 0000H During timer operation the contents of TM2C may not be read depending on the conditions of...

Page 146: ...er and the high order are set to 0000H When reading TM3C in 16 bit timer mode be sure to read TM2C first since the count value of TM3C is stored in the TM3C latch when TM2C is read During timer operat...

Page 147: ...ting the operation clock of timer 0 LSCLK HTBCLK or the external clock P44 T02P0CK can be selected by these bits T0CS1 T0CS0 Description 0 0 LSCLK initial value 0 1 HTBCLK 1 0 Prohibited timer 0 does...

Page 148: ...ite TM1CON0 while the timer 1 is stopped T1STAT of the TM1CON1 register is 0 Description of Bits T1CS1 T1CS0 bits 1 0 The T1CS1 and T1CS0 bits are used for selecting the operation clock of timer 1 LSC...

Page 149: ...nd T23M16 bit is used for selecting the operating mode of timer 2 and timer 3 In 8 bit timer mode each of timer 0 and timer 1 operates independently as a 8 bit timer In 16 bit timer mode timer 2 and t...

Page 150: ...ite TM3CON0 while the timer 3 is stopped T3STAT of the TM3CON1 register is 0 Description of Bits T3CS1 T3CS0 bits 1 0 The T3CS1 and T3CS0 bits are used for selecting the operation clock of timer 3 LSC...

Page 151: ...W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 TM0CON1 is a special function register SFR to control a timer 0 Description of Bits T0RUN bit 0 The T0RUN bit is used for controlling stop start of...

Page 152: ...to control a timer 1 Description of Bits T1RUN bit 0 The T1RUN bit is used for controlling count stop start of timer 1 In 16 bit timer mode be sure to set this bit to 0 Timer 1 is incremented caused b...

Page 153: ...cial function register SFR to control a timer 2 Description of Bits T2RUN bit 0 The T2RUN bit is used for controlling stop start of timer 2 Setting the T2RUN bit can forcely cancel the counting in the...

Page 154: ...3RUN bit 0 The T3RUN bit is used for controlling stop start of timer 3 In 16 bit timer mode and 16 bit timer frequency measurement mode be sure to set this bit to 0 Timer 3 is incremented caused by a...

Page 155: ...he TnRUN bits are set to 1 again TMn restart incremental counting from the previous values To initialize TMnC to 00H perform write operation in TMnC The timer interrupt period TTMI is expressed by the...

Page 156: ...s the operation timing in frequency measurement mode Figure 10 3 Operation Timing in frequency measurement mode 1 High speed clock HSCLK HTBCLK has to be in oscillating state by conrolling with FCONn...

Page 157: ...N1 of TM2C register and TM3C register For example of utilizing N1 to occur 9600Hz timer interrupt Assuming the HTBCLK is 600kHz N1 600000 437 32768 8001 Decimal 1F41 Hexadecimal 0001 1111 0100 0001 B...

Page 158: ...regiser and UA0BRTL register have to be set as follows See the previous secntion 10 3 2 and section 14 3 2 in UART chapter UA0BRTH UA0BRTL the frequency ratio of HTBCLK and 9600Hz 1 N1 128 1 N2 1 1 R...

Page 159: ...racy 300 Round off N1 4 2bit right shift minus 1 2 600 Round off N1 8 3bit right shift minus 1 1200 Round off N1 16 4bit right shift minus 1 2400 Round off N1 32 5bit right shift minus 1 4800 Round of...

Page 160: ...Chapter 11 PWM...

Page 161: ...PWM interrupt PW0INT occurs For the PWM clock a low speed clock LSCLK a high speed time base clock HTBCLK and an external clock are available 11 1 2 Configuration Figure 11 1 shows the configuration o...

Page 162: ...2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F0A0H PWM0 period register L PW0PL PW0P R W 8 16 0FFH 0F0A1H PWM0 period register H PW0PH R W 8 0FFH 0F0A2H PWM0 duty...

Page 163: ...P0P0 R W R W R W R W R W R W R W R W R W At reset 1 1 1 1 1 1 1 1 Address 0F0A1H Access R W Access size 8 bits Initial value 0FFH 7 6 5 4 3 2 1 0 PW0PH P0P15 P0P14 P0P13 P0P12 P0P11 P0P10 P0P9 P0P8 R...

Page 164: ...0 Address 0F0A2H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 PW0DH P0D15 P0D14 P0D13 P0D12 P0D11 P0D10 P0D9 P0D8 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Addre...

Page 165: ...H The data that is written is meaningless When data is read from PW0CL the value of PW0CH is latched When reading PW0CH and PW0CL use a word type instruction or pre read PW0CL The contents of PW0CH an...

Page 166: ...SCLK initial value 0 1 HTBCLK 1 0 Prohibited the PWM circuit does not operate 1 1 External clock P44 T02P0CK P0IS1 P0IS0 bits 3 2 The P0IS1 and P0IS0 bits are used to select the point at which the PWM...

Page 167: ...cription of Bits P0RUN bit 0 The P0RUN bit is used to control count stop start of PWM0 P0RUN Description 0 Stops counting Initial value 1 Starts counting P0FLG bit 6 The P0FLG bit is used to read the...

Page 168: ...counter registers stop counting after counting once the falling of the PWM clock P0CK Confirm that PW0CH and PW0CL are stopped by checking that the PnSTAT bit of the PWM0 control register 1 PW0CON1 is...

Page 169: ...peration Timing Diagram of PWM0 Note Even if 0 is written to the P0RUN bit counting operation continues up to the falling edge the PWM0 status flag P0STAT is in a 1 state of the next PWM clock pulse T...

Page 170: ...MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data 0 Set P43C1 bit bit3 of P4CON1 register to 1 set P43C0 bit bit3 of P4CON0 register to 1 and set P43DIR bit bit3 of P4DIR register to 0 for specifying...

Page 171: ...it bit4 of P3CON0 register to 1 and set P34DIR bit bit4 of P3DIR register to 0 for specifying the P34 as CMOS output Reg name P3CON1 register Address 0F21BH Bit 7 6 5 4 3 2 1 0 Bit name P35C1 P34C1 P3...

Page 172: ...Chapter 12 Watchdog Timer...

Page 173: ...al and shifts the mode to a system reset mode For interrupts see Chapter 5 Interrupts and for WDT interrupt see Chapter 3 Reset Function 12 1 1 Features Free running cannot be stopped One of four type...

Page 174: ...r 13 Watchdog Timer 12 2 12 2 Description of Registers 12 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F00EH Watchdog timer control register WDTCON R W 8 00H 0F00...

Page 175: ...ON d7 d0 bits 7 0 This bit is used to write data to clear the WDT counter Write 5AH on the condition of WDP is 0 and write 0A5H on the condition of WDP is 1 Note When the WDT interrupt WDTINT occurs b...

Page 176: ...W R W R W R W R W Initial value 0 0 0 0 0 0 1 0 WDTMOD is a special function register to set the overflow period of the watchdog timer Description of Bits WDT1 0 bits 1 0 These bits are used to select...

Page 177: ...cannot be cleared within the WDT counter overflow period TWOV a watchdog timer interrupt WDTINT occurs If the WDT counter is not cleared even by the software processing performed following the watchdo...

Page 178: ...timer interrupt request WDTINT is generated In this case the WDT counter and the internal pointer WDP are initialiaed for a half cycle of low speed clock about 15 26us If the WDT counter is not clear...

Page 179: ...d the low speed clock LSCLK starts oscillating If the WDT counter gets overflow the WDT non maskable interrupt occurs and then a system reset occurs Therefore it is needed to clear the WDT counter eve...

Page 180: ...Chapter 13 Synchronous Serial Port...

Page 181: ...ve selectable MSB first or LSB first selectable 8 bit length or 16 bit length selectable fro the data length 13 1 2 Configuration Figure 13 1 shows the configuration of the synchronous serial port SIO...

Page 182: ...O Description P40 SIN0 P44 SIN0 I Receive data input Used for the tertiary function of the P40 and P44 pins P41 SCK0 P45 SCK0 I O Synchronous clock input output Used for the tertiary function of the P...

Page 183: ...te Symbol Word R W Size Initial value 0F280H Serial port 0 transmit receive buffer L SIO0BUFL SIO0BUF R W 8 16 00H 0F281H Serial port 0 transmit receive buffer H SIO0BUFH R W 8 00H 0F282H Serial port...

Page 184: ...F281H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 SIO0BUFH S0B15 S0B14 S0B13 S0B12 S0B11 S0B10 S0B9 S0B8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 SIO0BUFL...

Page 185: ...ue 0 0 0 0 0 0 0 0 SIO0CON is a special function register SFR to control the synchronous serial port Description of Bits S0EN bit 0 The S0EN bit is used to specify start of synchronous serial communic...

Page 186: ...first S0MD1 S0MD0 bits 2 1 The S0MD1 and S0MD0 bits are used to select transmit receive or transmit receive mode of the synchronous serial port S0MD1 S0MD0 Description 0 0 Stops transmission receptio...

Page 187: ...to S0CK0 bits are used to select the transfer clock of the synchronous serial port When the internal clock is selected this LSI is set to master mode and when the external clock is selected it is set...

Page 188: ...the serial port mode register SIO0MOD1 the LSI is set to a master mode and when an external clock P41 SCK0 or P45 SCK0 is selected the LSI is set to a slave mode The serial port mode register SIO0MOD...

Page 189: ...ave mode The serial port mode register SIO0MOD0 enables selection of MSB first or LSB first The receive data input pin P40 SIN0 or P44 SIN0 and transfer clock input output pin P41 SCK0 or P45 SCK0 mus...

Page 190: ...f GPIO When an internal clock is selected in the serial port mode register SIO0MD1 the LSI is set to a master mode and when an external clock P41 SCK0 or P45 SCK0 is selected the LSI is set ot a slave...

Page 191: ...f P4CON1 register to 1 set P42C0 P41C0 bits bit2 bit1 of P4CON0 register to 1 and set P42DIR P41DIR bits bit2 bit1 of P4DIR register to 0 for specifying the P42 P41 as CMOS output Set P40DIR bit bit0...

Page 192: ...of P4DIR register to 0 for specifying the P42 as CMOS output Set P41DIR P40DIR bits bit1 0 of P4DIR register to 1 for specifying the P41 and P40 as input pins Data setting to P41C1 bit P40C1 bit P41C0...

Page 193: ...6 bit5 of P4DIR register to 0 for specifying the P46 P45 as CMOS output Set P44DIR bit bit4 of P4DIR register to 1 for specifying the P44 as an input pin Data setting to P44C1 bit and P44C0 bit depend...

Page 194: ...of P4DIR register to 0 for specifying the P46 as CMOS output Set P45DIR P44DIR bits bit5 4 of P4DIR register to 1 for specifying the P45 and P44 as input pins Data setting to P45C1 bit P44C1 bit P45C0...

Page 195: ...Chapter 14 UART...

Page 196: ...e as communication logic LSB first or MSB first slectable as a communication direction Communication speed Settable within the range of 200bps to 115200bps Built in baud rate generator 14 1 2 Configur...

Page 197: ...value 0F290H UART0 transmit receive buffer UA0BUF R W 8 00H 0F291H UART0 control register UA0CON R W 8 00H 0F292H UART0 mode register 0 UA0MOD0 UA0MOD R W 8 16 00H 0F293H UART0 mode register 1 UA0MOD1...

Page 198: ...a to UA0BUF after making sure that the U0FUL flag of the UART0 status register UA0STAT is 0 Any value written to UA0BUF can be read In receive mode since data received at termination of reception is s...

Page 199: ...ial function register SFR to start stop communication of the UART Description of Bits U0EN bit 0 The U0EN bit is used to specify the UART communication operation start When U0EN is set to 1 UART commu...

Page 200: ...ct the clock to be input to the baud rate generator of the UART0 U0CK1 U0CK0 Description 0 0 LSCLK initial value 0 1 LSCLK 2 1 HSCLK U0RSEL bit 4 The U0RSEL bit is used to select the receive data inpu...

Page 201: ...he communication of the UART U0LG1 U0LG0 Description 0 0 8 bit length initial value 0 1 7 bit length 1 0 6 bit length 1 1 5 bit length U0PT1 U0PT0 bits 3 2 The U0PT1 and U0PT0 bits are used to select...

Page 202: ...0DIR bit 6 The U0DIR bit is used to select LSB first or MSB first in the communication of the UART U0DIR Description 0 LSB first initial value 1 MSB first Note Always set the UA0MOD1 register while co...

Page 203: ...ess R W Access size 8 bits Initial value 0FH 7 6 5 4 3 2 1 0 UA0BRTH U0BR11 U0BR10 U0BR9 U0BR8 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 1 1 1 1 UA0BRTL and UA0BRTH are special functio...

Page 204: ...ing error initial value 1 Framing error U0OER bit 1 The U0OER bit is used to indicate occurrence of an overrun error of the UART If the received data in the transmit receive buffer UA0BUF is received...

Page 205: ...ansmit mode this bit is set to 1 and when transmit data is transferred to the shift register this bit is set to 0 To transmit data consecutively write the next transmit data to UA0BUF after checking t...

Page 206: ...l these options are set with the UART0 mode register UA0MOD1 Figure 14 2 and Figure 14 3 show the positive logicc input output format and negative logic input output format respectively Figure 14 2 Po...

Page 207: ...0CK1 U0CK0 Count value Period of 1 bit UA0BRTH UA0BRTL 1200 bps 32 768 kHz 0 0 27 Approx 824 s 00H 1AH 2400 bps 65 536 kHz 0 1 27 Approx 412 s 00H 1AH 4800 bps 4 096 MHz 1 853 Approx 208 s 03H 054H 96...

Page 208: ...from the TXD0 pin U0B6 U0B3 U0B7 U0B5 U0B2 U0B1 U0B4 U0B0 LSB reception LSB reception Data length 8 bits Data length 7 bits Data length 6 bits U0B7 is 0 at completion of reception Data length 5 bits M...

Page 209: ...put a UART0 interrupt is requested In the UART0 interrupt routine the next data to be transmitted is written to the transmit receive buffer UA0BUF When the next data to be transmitted is written to th...

Page 210: ...UA0BUF write instruction U0EN set instruction 1st data 2nd data BRT BRT Start 0 1 2 7 Parity Stop Start 0 1 2 7 Parity Stop Transmit receive buffer write enable period Transmit receive buffer write e...

Page 211: ...ata and parity bit are shifted into the shift register and 5 to 8 bit receive data is transferred to the transmit receive buffer UA0BUF concurrently with the fall of the internal transfer clock of The...

Page 212: ...7 Parity Stop Parity Stop Start 0 1 2 7 1st data 2nd data Parity error Overrun error Detection of start bit Detection of Parity error overrun error and framing error Request for UART0 interrupt Recep...

Page 213: ...gister to 1 set P43C0 bit bit3 of P4CON0 register to 1 and set P43DIR bit bit3 of P4DIR register to 0 for specifying the P43 as CMOS output Set P42DIR bit bit2 of P4DIR register to 1 for specifying th...

Page 214: ...7MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data 1 Set P43C1 bit bit3 of P4CON1 register to 1 set P43C0 bit bit3 of P4CON0 register to 1 and set P43DIR bit bit3 of P4DIR register to 0 for sp...

Page 215: ...UART function so don t care the data for the function Reg name P0D register Address 0F204H Bit 7 6 5 4 3 2 1 0 Bit name P03D P02D P01D P00D Data Bit not related to the UART using P43 and P02 function...

Page 216: ...Chapter 15 I2 C Bus Interface...

Page 217: ...multi master and clock synchronization handshake 15 1 2 Configuration Figure 15 1 shows the configuration of the I2 C bus interface I2C0RD I 2 C bus 0 receive register I2C0SA I 2 C bus 0 slave addres...

Page 218: ...ymbol Word R W Size Initial value 0F2A0H I 2 C bus 0 receive register I2C0RD R 8 00H 0F2A1H I 2 C bus 0 slave address register I2C0SA R W 8 00H 0F2A2H I 2 C bus 0 transmit data register I2C0TD R W 8 0...

Page 219: ...ve data I2C0RD is updataed after completion of each reception Description of Bits I20R7 I20R0 bits 7 0 The I20R7 to I20R0 bits are used to store receive data The signal input to the SDA pin is receive...

Page 220: ...R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C0SA is a special function register SFR to set the address and the transmit receive mode of the slave device Description of Bits I20RW bit...

Page 221: ...A2H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 I2C0TD is a...

Page 222: ...te I20EN 1 When the I20SP bit is set to 1 the I20ST bit is set to 0 I20ST Description 0 Stops communication initial value 1 Starts communication I20SP bit 1 The I20SP bit is a write only bit used to r...

Page 223: ...I20DW0 bits 3 2 The I20DW1 and I20DW0 bits are used to set the communication speed reduction rate of the I2 C bus interface Set this bit so that the communication speed does not exceed 100kpbs 400kpbs...

Page 224: ...0 I 2 C bus free state Initial value 1 I 2 C bus busy state I20ACR bit 1 The I20ACR bit is used to store the acknowledgment signal received Acknowledgment signals are received each time the slave addr...

Page 225: ...I2C0CON setting wait state control register setting wait state The value of I2C0SA output from the SDA pin is stored in I2C0RD during aftermentioned Control Register Setting Wait State 15 3 1 4 Data...

Page 226: ...r receive mode When 1 is written to the I20SP bit the LSI shifts to the stop condition When 1 is written to the I20RS bit and I20ST bit the operation shifts to the repeated start condition 15 3 1 7 St...

Page 227: ...7 A Receive data Value of I2C0SA S r S P S r Transmission Reception Start condition Stop condition Repeated start condition Reception of acknowledgment Transmission of acknowledgment Transmission of n...

Page 228: ...e output until termination of the subsequent byte data communication I20ER bit is initialized to 0 by writing I2 C Bus 0 Control Register I2C0COCON Figure 15 6 shows the operation timing and control m...

Page 229: ...tion 40 18 22 4 18 22 18 18 22 10 reduction 44 20 24 4 20 24 20 20 24 20 reduction 48 22 26 4 22 26 22 22 26 30 reduction 52 24 28 4 24 28 24 24 28 Fast mode 400 k No reduction 10 4 6 2 4 6 4 4 6 10 r...

Page 230: ...t bit1 0 of P4CON1 register to 1 set P41C0 P40C0 bit bit1 0 of P4CON0 register to 0 and set P41DIR P40DIR bit bit1 0 of P4DIR register to 0 for specifying the P41 and P40 as Nch open drain output The...

Page 231: ...Chapter 16 NMI Pin...

Page 232: ...ows selection of an input with a pull up resistor or a high impedance input Applies a noise filter to NMI interrupt NMINT 16 1 2 Configuration Figure 16 1 shows the configuration of the NMI pin NMID N...

Page 233: ...l Chapter 16 NMI Pin 16 2 16 2 Description of Registers 16 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F200H NMI data register NMID R 8 Depends on pin state 0F20...

Page 234: ...ss size 8 bits Initial value Depends on the pin state 7 6 5 4 3 2 1 0 NMID NMI R R R R R R R R R Initial value 0 0 0 0 0 0 0 x NMID is a read only special function register SFR for reading the NMI pin...

Page 235: ...2 1 0 NMICON NMIC R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 NMICON is a special function register SFR to select the input mode of the NMI pin Description of Bits NMIC bit 0 Th...

Page 236: ...t the input mode with a pull up resistor is selected The level of the NMI pin can be read by reading the NMI data register MMID 16 3 1 Interrupt Request When a level change occurs at the NMI pin after...

Page 237: ...Chapter 17 Port 0...

Page 238: ...an be used as the RXD0 input pin of UART0 17 1 2 Configuration Figure 17 1 shows the configuration of Port 0 P0D Port 0 data register P0CON0 Port 0 control register 0 P0CON1 Port 0 control register 1...

Page 239: ...itial value 0F204H Port 0 data register P0D R 8 Depends on pin status 0F206H Port 0 control register 0 P0CON0 P0CON R W 8 16 00H 0F207H Port 0 control register 1 P0CON1 R W 8 00H 0F020H External inter...

Page 240: ...0 0 x x x x P0D is a special function register SFR to only read the pin level of Port 0 Description of Bits P03D P00D bits 3 0 The P03D to P00D bits are used to read the pin level of Port 0 P00D Desc...

Page 241: ...0 0 0 0 0 0 P0CON0 and P0CON1 are special function registers SFRs to select the input mode of Port 0 Description of Bits P03C0 P00C0 P03C1 P00C1 bits 3 0 The P03C0 to P00C0 bits and the P03C1 to P00C1...

Page 242: ...al value 0 0 0 0 0 0 0 0 EXICON0 and EXICON1 are special function registers SFRs to select an interrupt edge of Port 0 Description of Bits P03E0 P00E0 P03E1 P00E1 bits 3 0 The P03E0 to P00E0 bits and...

Page 243: ...me base counter LTBC P00SM Description 0 Detects the input signal edge for a P00 interrupt without sampling initial value 1 Detects the input signal edge for a P00 interrupt with sampling P01SM Descri...

Page 244: ...can be used as the trigger input for the capture circuit and the P02 pin can be used as the RXD0 input pin of UART0 For the capture function and the UART function see Chapter 8 Capture and Chapter 14...

Page 245: ...Both Edge Interrupt Mode without Sampling is Selected d When Rising Edge Interrupt Mode with Sampling is Selected Figure 17 2 P00 to P03 Interrupt Generation Timing SYSCLK P0n pin P0nINT Interrupt req...

Page 246: ...Chapter 18 Port 1...

Page 247: ...with a pull down resistor or input mode with a pull up resistor for each bit Allows selection of a high speed crystal ceramic resonator pin or an external clock input pin as a secondary function 18 1...

Page 248: ...cription of Registers 18 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F208H Port 1 data register P1D R 8 Depends on pin status 0F20AH Port 1 control register 0 P1...

Page 249: ...R R R R R R R R Initial value 0 0 0 0 0 0 x x P1D is a special function register SFR dedicated to read the input level of the Port 1 pin Description of Bits P11D P10D bits 1 0 The P11D and P10D bits...

Page 250: ...used to select high impedance input mode input mode with a pull down resistor or input mode with a pull up resistor P11C1 P11C0 Description 0 0 P11 pin high impedance input mode initial value 0 1 P11...

Page 251: ...ect high speed crystal ceramic oscillation mode or external clock input mode by using the high speed clock mode select function of the OSCM1 and 0 bits of the frequency control register 0 FCON0 In cry...

Page 252: ...Chapter 19 Port 2...

Page 253: ...output mode for each bit Allows output of low speed clock LSCLK high speed clock OUTCLK or melody 0 MD0 as a secondary function 19 1 2 Configuration Figure 19 1 shows the configuration of Port 2 P2D...

Page 254: ...gisters 19 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F210H Port 2 data register P2D R W 8 00H 0F212H Port 2 control register 0 P2CON0 P2CON R W 8 16 00H 0F213H...

Page 255: ...register SFR to set the output value of Port 2 The value of this register is output to Port 2 The value written to P2D is readable Description of Bits P22D P20D bits 2 0 The P22D to P20D bits are use...

Page 256: ...P22C1 to P20C1 bits are used to select high impedance output mode P channel open drain output mode N channel open drain output mode or CMOS output mode To directly drive LEDs select N channel open dr...

Page 257: ...output port function initial value 1 Melody 0 MD0 output function P21MD bit 1 The P21MD bit is used to select the primary function or the secondary function of the P21 pin P21MD Description 0 General...

Page 258: ...ontrol registers 0 and 1 P2CON0 and P2CON1 At a system reset high impedance output mode is selected as the initial state Depending of the value set in the Port 2 data register P2D a L level or H level...

Page 259: ...Chapter 20 Port 3...

Page 260: ...s selection of high impedance input input with a pull down resistor or input with a pull up resistor in input mode for each bit The RC ADC channel 0 oscillation pins IN0 CS0 RS0 RT0 RCT0 RCM and the P...

Page 261: ...31 CS0 I O Input output port Reference capacitor connection pin for RC ADC P32 RS0 I O Input output port Reference resistor connection pin for RC ADC P33 RT0 I O Input output port Resistor sensor conn...

Page 262: ...yte Symbol Word R W Size Initial value 0F218H Port 3 data register P3D R W 8 00H 0F219H Port 3 direction register P3DIR R W 8 00H 0F21AH Port 3 control register 0 P3CON0 P3CON R W 8 16 00H 0F21BH Port...

Page 263: ...g the port direction register P3DIR described later Description of Bits P35D P30D bits 5 0 The P35D to P30D bits are used to set the output value of the Port 3 pin in output mode and to read the pin l...

Page 264: ...input output mode of Port 3 Description of Bits P35DIR P30DIR bits 5 0 The P35DIR to P30DIR pins are used to set the input output direction of the Port 3 pin P35DIR Description 0 P35 pin Output initia...

Page 265: ...re used to select high impedance output P channel open drain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or inpu...

Page 266: ...r 1 0 P32 pin N channel open drain output P32 pin Input with a pull up resistor 1 1 P32 pin CMOS output P32 pin High impedance input When output mode is selected P31DIR bit 0 When input mode is select...

Page 267: ...P35MD1 and P35MD0 bits are used to select the primary or secondary function of the P35 pin P35MD1 P35MD0 Description 0 0 General purpose input output mode initial value 0 1 RC oscillation monitor pin...

Page 268: ...MD1 and P30MD0 bits are used to select the primary or secondary function of the P30 pin P30MD1 P30MD0 Description 0 0 General purpose input output mode initial value 0 1 RC oscillation waveform input...

Page 269: ...cted as the initial state In output mode L or H level is output to each pin of Port 3 depending on the value set by the Port 3 data register P3D In input mode the input level of each pin of Port 3 can...

Page 270: ...Chapter 21 Port 4...

Page 271: ...bit in input mode The P44 and P45 pins can be used as external clock input pins for the timer and PWM The I2C bus interface pins SDA SCL UART pins RXD0 TXD0 RC ADC channel 1 oscillation pins IN1 CS1 R...

Page 272: ...input pin SSIO0 data output pin P43 TXD0 PWM0 I O Input output port UART0 data output pin PWM0 output pin P44 T02P0CK IN1 SIN0 I O Input output port Timer 0 Timer 2 PWM0 external clock RC oscillation...

Page 273: ...yte Symbol Word R W Size Initial value 0F220H Port 4 data register P4D R W 8 00H 0F221H Port 4 direction register P4DIR R W 8 00H 0F222H Port 4 control register 0 P4CON0 P4CON R W 8 16 00H 0F223H Port...

Page 274: ...P47D to P40D bits are used to set the output value of the Port 4 pin in output mode and to read the pin level of the Port 4 pin in input mode P47D Description 0 Output or input level of the P47 pin L...

Page 275: ...IR bits 7 0 The P47DIR to P40DIR pins are used to set the input output direction of the Port 4 pin P47DIR Description 0 P47 pin Output initial value 1 P47 pin Input P46DIR Description 0 P46 pin Output...

Page 276: ...ut mode and to select high impedance input input with a pull down resistor or input with a pull up resistor in input mode Setting of P47 pin When output mode is selected P47DIR bit 0 When input mode i...

Page 277: ...ected P42DIR bit 0 When input mode is selected P42DIR bit 1 P42C1 P42C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down...

Page 278: ...7 The P47MD1 and P47MD0 bits are used to select the primary or secondary function of the P47 pin P47MD1 P47MD0 Description 0 0 General purpose input output mode initial value 0 1 Resistor sensor conne...

Page 279: ...ut pin 1 0 SIO0 data output pin 1 1 Prohibited P41MD1 P41MD0 bit 1 The P41MD1 and P41MD0 bits are used to select the primary secondary or tertiary function of the P41 pin P41MD1 P41MD0 Description 0 0...

Page 280: ...ML610421 User s Manual Chapter 21 Port 4 21 10 When using RC ADC as the secondary function specify each pin be High impedance input even the RC oscillation monitor pin Pull up or Pull down input makes...

Page 281: ...In output mode L or H level is output to each pin of Port 4 depending on the value set by the Port 4 data register P4D In input mode the input level of each pin of Port 4 can be read from the Port 4 d...

Page 282: ...Chapter 22 Port A...

Page 283: ...or input with a pull up resistor for each bit in input mode 22 1 2 Configuration Figure 22 1 shows the configuration of Port A PAD Port A data register PADIR Port A direction register PACON0 Port A c...

Page 284: ...ters 22 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F250H Port A data register PAD R W 8 00H 0F251H Port A direction register PADIR R W 8 00H 0F252H Port A contr...

Page 285: ...PA7D to PA0D bits are used to set the output value of the Port A pin in output mode and to read the pin level of the Port A pin in input mode PA7D Description 0 Output or input level of the PA7 pin L...

Page 286: ...R bits 7 0 The PA7DIR to PA0DIR pins are used to set the input output direction of the Port A pin PA7DIR Description 0 PA7 pin Output initial value 1 PA7 pin Input PA6DIR Description 0 PA6 pin Output...

Page 287: ...t mode and to select high impedance input input with a pull down resistor or input with a pull up resistor in input mode Setting of PA7 pin When output mode is selected PA7DIR bit 0 When input mode is...

Page 288: ...ected PA2DIR bit 0 When input mode is selected PA2DIR bit 1 PA2C1 PA2C0 Description 0 0 High impedance output initial value High impedance input 0 1 P channel open drain output Input with a pull down...

Page 289: ...be selected by setting the Port A control registers 0 and 1 PACON0 and PACON1 In input mode high impedance input mode input mode with a pull down resistor or input mode with a pull up resistor can be...

Page 290: ...Chapter 23 Melody Driver...

Page 291: ...es 8 frequencies and 15 duties can be set 23 1 2 Configuration Figure 23 1 shows the configuration of the melody driver MD0CON Melody 0 control register MD0TMP Melody 0 tempo code register MD0TON Melo...

Page 292: ...2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F2C0H Melody 0 control register MD0CON R W 8 00H 0F2C1H Melody 0 tempo code register MD0TMP R W 8 00H 0F2C2H Melody 0...

Page 293: ...trol a melody and the buzzer Description of Bits BZMD bit 1 The BZMD bit is used to select melody mode or buzzer mode BZMD Description 0 Melody mode initial value 1 Buzzer mode M0RUN bit 0 The M0RUN b...

Page 294: ...and the output mode of a buzzer sound waveform when buzzer mode is selected Description of Bits M0TM3 M0TM2 M0TM1 M0TM0 bits 3 0 When melody mode is selected BZMD bit 0 M0TM3 M0TM2 M0TM1 M0TM0 Descrip...

Page 295: ...y when melody mode is selected and a buzzer output frequency when buzzer mode is selected Description of Bits M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 bits 6 0 When melody mode is selected BZMD bit 0...

Page 296: ...ion of Bits M0LN5 M0LN4 M0LN3 M0LN2 M0LN1 M0LN0 bits 5 0 When melody mode is selected BZMD bit 0 M0LN5 to 0 Description Sets the corresponding tone length code For tone length codes see Section 23 3 3...

Page 297: ...ssigned as the secondary function of Port 2 See Chapter 19 Port 2 for the secondary function settings of Port 2 In the software processing after melody 0 interrupt the tone length code and the scale c...

Page 298: ...ts are set to 0 is equal to the shortest tone length the tempo when the only M0TP0 bit is set to 1 Table 23 1 Correspondence between Tempos and Tempo Codes Tempo Tempo code MD0TMP M0TP3 M0TP2 M0TP1 M0...

Page 299: ...LN5 M0LN4 M0LN3 M0LN2 M0LN1 M0LN1 M0LN5 0 1 1 1 1 1 1 3FH 1 0 1 1 1 1 2FH 0 1 1 1 1 1 1FH 0 1 0 1 1 1 17H 0 0 1 1 1 1 0FH 0 0 1 0 1 1 0BH 0 0 0 1 1 1 07H 0 0 0 1 0 1 05H 0 0 0 0 1 1 03H 0 0 0 0 1 0 02...

Page 300: ...odes Scale Frequency Hz Scale code MD0TON M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 M0TN6 0 C 1 529 1 1 1 1 0 1 1 7BH Cis 1 560 1 1 1 0 1 0 0 74H D 1 590 1 1 0 1 1 1 0 6EH Dis 1 624 1 1 0 1 0 0 0 68H...

Page 301: ...Table 23 4 Note Codes of Melody Examples Note Note code MD0LEN MD0TON hexadecimal 5 4 3 2 1 0 6 5 4 3 2 1 0 G 2 1 0 1 1 1 1 0 1 0 1 0 0 0 2F28H D 2 0 0 1 1 1 1 0 1 1 0 1 0 1 0F35H G 2 0 0 1 1 1 1 0 1...

Page 302: ...D0TON 5 Set bit 2 ENMLT of the frequency control register 1 FCON1 to 1 to enable the 2 low speed clock 6 When the M0RUN bit of the melody 0 control register MD0CON is set to 1 the waveform equivalent...

Page 303: ...2 as CMOS output Reg name P2CON1 register Address 0F213H Bit 7 6 5 4 3 2 1 0 Bit name P22C1 P21C1 P20C1 Data 1 Reg name P2CON0 register Address 0F212H Bit 7 6 5 4 3 2 1 0 Bit name P22C0 P21C0 P20C0 Da...

Page 304: ...Chapter 24 RC Oscillation Type A D Converter...

Page 305: ...easurement range or measurement at two points For input clock see Chapter 6 Clock Generation Circuit 24 1 1 Features 2 channel system by time division 24 1 2 Configuration The RC ADC consists of two R...

Page 306: ...Channel 0 Used for the secondary function of the P33 pin P34 RCT0 O Pin for connection with a resistive capacitive sensor for measurement on Channel 0 Used for the secondary function of the P34 pin P3...

Page 307: ...e 0F300H RC ADC Counter A register 0 RADCA0 R W 8 00H 0F301H RC ADC Counter A register 1 RADCA1 R W 8 00H 0F302H RC ADC Counter A register 2 RADCA2 R W 8 00H 0F304H RC ADC Counter B register 0 RADCB0...

Page 308: ...W Initial value 0 0 0 0 0 0 0 0 Address 0F302H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 RADCA2 RAA23 RAA22 RAA21 RAA20 RAA19 RAA18 RAA17 RAA16 R W R W R W R W R W R W R W R W R...

Page 309: ...W Initial value 0 0 0 0 0 0 0 0 Address 0F306H Access R W Access size 8 bits Initial value 00H 7 6 5 4 3 2 1 0 RADCB2 RAB23 RAB22 RAB21 RAB20 RAB19 RAB18 RAB17 RAB16 R W R W R W R W R W R W R W R W R...

Page 310: ...1 CS0 oscillation mode 0 1 0 0 RS0 CT0 oscillation mode 0 1 0 1 RS1 CS1 oscillation mode 0 1 1 0 RT1 CS1 oscillation mode 0 1 1 1 IN1 pin external clock input mode 1 Setting prohibited RADI bit 4 The...

Page 311: ...of the RC ADC When RARUN is set to 1 A D conversion starts If Counter A or Counter B overflows with RARUN set to 1 the bit is automatically reset to 0 RARUN is set to 0 at system reset RARUN Descripti...

Page 312: ...ndary functions of Port 3 see Chapter 20 Port 3 for the secondary functions of Port 4 see Chapter 21 Port 4 24 3 1 RC Oscillator Circuits RC ADC performs A D conversion by converting the oscillation f...

Page 313: ...cillation The value of kRCCLK slightly changes depending on the value of the supply voltage VDD RI R or C Table 24 2 lists the typical kRCCLK values Table 24 2 Typical Values of the Proportional Const...

Page 314: ...OM3 OM2 OM1 OM0 Mode of oscillation 0 0 0 1 Oscillates with the reference resistor RS0 and CS0 0 0 1 0 Oscillates with the sensor RT0 and CS0 0 0 1 1 Oscillates with the reference resistor RT0 1 and C...

Page 315: ...In this mode a gate time is determined by Counter B and the RC oscillator clock RCCLK and the base clock BSCLK which is used as the time reference is counted by Counter A within the gate time to make...

Page 316: ...due to overflow of Counter A RC oscillation stops and Counter B stops counting The final count value nB0 of Counter B is the RCCLK count value during the gate time nA0 tBSCLK and is expressed by the...

Page 317: ...l by Counter B overflow Set the RARUN bit of RADCON to 1 to start A D conversion When the RARUN bit is set to 1 and the RCON signal signal synchronized with the fall of the base clock is set to 1 the...

Page 318: ...A1 tBSCLK nA1 tBSCLK 1000000H nB1 1 2 0FFFFFEH 0FFFFFFH 000000H nB1 tRCCLK Gate time Interrupt request tRCCLK RARUN BSCLK RCON Counter A RC oscillator circuit Input waveform IN0 IN1 RCCLK Counter B RA...

Page 319: ...nT0 K RT0 K f T Figure 24 9 Temperature Characteristics of Thermistor RT0 is expressed as a function of temperature T by the following equation RT0 f T Figure 24 10 shows the ideal characteristics of...

Page 320: ...ing these resistances will be like the solid lines in Figures 24 12 and 24 13 however in reality it would appear that they will be like the dotted lines due to error factors such as IC temperature cha...

Page 321: ...equencies of them is used as described above In the example below operation for these two steps is performed using the following combination First step RC oscillation with RS0 in Counter A reference m...

Page 322: ...de Counter B reference mode 0 366 sec nA0 tBSCLK nB0 tRCCLK RS0 nB0 tRCCLK RT0 nA1 tBSCLK Increments by BSCLK CNTA2 0 000000H 00000H Increments by BSCLK nA1 0FFFB50H Increments by RCCLK RS0 CNTB2 0 00...

Page 323: ...rsion operation stops section c RARUN bit 0 At this time Counter A is set to 000000H The content of Counter B at this time is expressed by the following expression nB0 nA0 tBSCLK Expression B tRCCLK R...

Page 324: ...program according to the temperature to resistance characteristics of the themistor 24 3 4 Monitoring RC Oscillation The RC oscillator clock RCCLK can be output using the secondary function of the P3...

Page 325: ...register to 0 and set P34DIR P30DIR bit bit4 0 of P3DIR register to 1 for specifying the P34 P30 as high impedance inputs The P34C1 P30C1 bit and P34C0 P30C0 bit can be set to all 1 instead of all 0 t...

Page 326: ...P47 P44 as high impedance inputs The P47C1 P44C1 bit and P47C0 P44C0 bit can be set to all 1 instead of all 0 to select the high impedance inputs Reg name P4CON1 register Address 0F223H Bit 7 6 5 4 3...

Page 327: ...Chapter 25 Successive Approximation Type A D Converter...

Page 328: ...h enables channel selection from 2 channels 25 1 2 Configuration Figure 25 1 shows the configuration of SA ADC SADR0L SA ADC result register 0L SADR0H SA ADC result register 0H SADR1L SA ADC result re...

Page 329: ...power supply pin for the successive approximation type A D converter VREF Reference power supply pin for the successive approximation type A D converter AVSS Negative power supply pin for the successi...

Page 330: ...R W Size Initial value 0F2D0H SA ADC result register 0L SADR0L SADR0 R 8 16 00H 0F2D1H SA ADC result register 0H SADR0H R 8 00H 0F2D2H SA ADC result register 1L SADR1L SADR1 R 8 16 00H 0F2D3H SA ADC...

Page 331: ...its SAR03 SAR00 bits 7 4 The SAR03 SAR00 bits are used to store the values of bit 3 to bit 0 of A D conversion results 12 bits on channel 0 25 2 3 SA ADC Result Register 0H SADR0H Address 0F2D1H Acces...

Page 332: ...Bits SAR13 SAR10 bits 7 4 The SAR13 SAR10 bits are used to store the values of bit 3 to bit 0 of A D conversion results 12 bits on channel 1 25 2 5 SA ADC Result Register 1H SADR1H Address 0F2D3H Acce...

Page 333: ...onsecutively When this bit is set to 0 A D conversion is performed once only for each channel and when it is set to 1 A D conversion is performed consecutively according to the settings of the SA ADC...

Page 334: ...version When SALP of SADCON0 is 0 and then A D conversion on the channel with the largest channel number among the selected ones is terminated the SARUN bit is automatically set to 0 Notes Use the SA...

Page 335: ...l 0 SACH1 bit 1 SACH1 Description 0 Stops conversion on channel 1 Initial value 1 Performs conversion on channel 1 The SACH1 and SACH0 bits are used to select channel s on which A D conversion is perf...

Page 336: ...SADR1 AIN1 input The values of the result register for the sections with a slash mark remain unchanged Do not start A D conversion when bits 1 SACH1 or 0 SACH0 of SA ADC mode register 0 SADMOD0 is 0...

Page 337: ...results are stored in the applicable SA ADC result registers SADRnL SADRnH and when A D conversion of the largest channel number that is selected terminates an SA ADC conversion termination interrupt...

Page 338: ...Chapter 26 LCD Drivers...

Page 339: ...programmable allocation function The programmable display allocation function only generates table data can be used for the type 3 When not using the display allocation register A and B Set DASN bit o...

Page 340: ...t units by programming according to the contents of display allocation registers A and B Therefore the display register array can be changed in flexible and simplify the software process for display C...

Page 341: ...1 1 to 1 16 duty 1 3 and 1 4 bias 4 types Frame frequency selectable 4 types Bias voltage multiplying clock selectable 8 types Contrast adjustment 1 3 bias 32 steps 1 4 bias 20 steps Programmable disp...

Page 342: ...1 DSPCON Display control register DSmCnA Allocation register A m 0 to 63 n 0 to 7 DSmCnB Allocation register B m 0 to 63 n 0 to 7 DSPR00 to DSPR71 Display registers Figure 26 4 Configuration of LCD D...

Page 343: ...gure 26 5 shows the configurations of the bias generation circuit with 1 3 bias and with 1 4 bias Figure 26 5 Configuration of Bias Generation Circuit Note When using 1 3 bias connect the VL2 pin and...

Page 344: ...nnection pin for LCD bias generation C2 Capacitor connection pin for LCD bias generation C3 Capacitor connection pin for LCD bias generation C4 Capacitor connection pin for LCD bias generation COM0 O...

Page 345: ...EG10 O LCD segment pin SEG11 O LCD segment pin SEG12 O LCD segment pin SEG13 O LCD segment pin SEG14 O LCD segment pin SEG15 O LCD segment pin SEG16 O LCD segment pin SEG17 O LCD segment pin SEG18 O L...

Page 346: ...pin SEG35 O LCD segment pin SEG36 O LCD segment pin SEG37 O LCD segment pin SEG38 O LCD segment pin SEG39 O LCD segment pin SEG40 O LCD segment pin SEG41 O LCD segment pin SEG42 O LCD segment pin SEG4...

Page 347: ...play contrast register DSPCNT R W 8 00H 0F0F2H Display mode register 0 DSPMOD0 DSPMOD R W 8 16 00H 0F0F3H Display mode register 1 DSPMOD1 R W 8 00H 0F0F4H Display control register DSPCON R W 8 00H 0F1...

Page 348: ...1 the bias generation circuit generates the LCD drive voltages VL1 to VL4 BSON Description 0 Bias circuit Off initial value 1 Bias circuit On BSN2 BSN0 bits 3 1 The BSN2 to BSN0 bits are used to sele...

Page 349: ...sed to adjust the contrast of display 32 steps LCN4 LCN3 LCN2 LCN1 LCN0 Description VL1 voltage typ V 0 0 0 0 0 Low 0 94 initial value 0 0 0 0 1 0 96 0 0 0 1 0 0 98 0 0 0 1 1 1 00 0 0 1 0 0 1 02 0 0 1...

Page 350: ...r SFR to control the display mode of the LCD drivers Description of Bits DUTY4 DUTY0 bits 4 0 The DUTY4 to DUTY0 bits are used to specify the duty in 16 steps 1 1 to 1 16 DUTY4 DUTY3 DUTY2 DUTY1 DUTY0...

Page 351: ...quency 102Hz 1 1 duty 64 00 73 14 85 33 102 40 1 2 duty 64 00 73 14 85 33 102 40 1 3 duty 64 25 73 31 85 33 103 04 1 4 duty 64 00 73 14 85 33 102 40 1 5 duty 64 25 73 64 86 23 102 40 1 6 duty 64 25 73...

Page 352: ...nd DADM0 are used to select a type of display register segment map Two types are available type 2 and type 3 type 1 is not available on ML610Q421 ML610Q422 ML610421 See section 26 2 9 and section 26 3...

Page 353: ...LCD display mode and all LCDs on mode can be selected In LCD stop mode Vss level is output to all the common drivers and segment drivers The charge and discharge current to and from the display panel...

Page 354: ...ion function Each valid bit of DSmCnA becomes undefined at system reset When the programmable display allocation function is not used DASN bit of DSPMOD1 reigster is reset to 0 DSmCnA can be used as d...

Page 355: ...1 a0 R W SEG49 COM1 DS49C1A 0F471H a7 a6 a5 a4 a3 a2 a1 a0 R W SEG0 COM2 DS0C2A 0F480H a7 a6 a5 a4 a3 a2 a1 a0 R W SEG49 COM2 DS49C2A 0F4B1H a7 a6 a5 a4 a3 a2 a1 a0 R W SEG0 COM3 DS0C3A 0F4C0H a7 a6 a...

Page 356: ...le display allocation function is not used DASN bit of DSPMOD1 reigster is reset to 0 DSmCnB can be used as data memory space 512 byte RAM Table 26 3 shows a list of display allocation register B Desc...

Page 357: ...1 b0 R W SEG49 COM1 DS49C1B 0F671H b7 b6 b5 b4 b3 b2 b1 b0 R W SEG0 COM2 DS0C2B 0F680H b7 b6 b5 b4 b3 b2 b1 b0 R W SEG49 COM2 DS49C2B 0F6B1H b7 b6 b5 b4 b3 b2 b1 b0 R W SEG0 COM3 DS0C3B 0F6C0H b7 b6 b...

Page 358: ...al function registers SFRs to store display data Each valid bit of DSPRxx becomes undefined at system reset The display registers that are not used for LCD display can be used for data memories Set da...

Page 359: ...c9 c8 R W DSPR16 0F116H SEG11 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR17 0F117H c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR18 0F118H SEG12 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR19 0F119H c15 c14 c13 c12 c11 c10 c9 c8 R...

Page 360: ...R W DSPR48 0F148H SEG36 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR49 0F149H c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR4A 0F14AH SEG37 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR4B 0F14BH c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR...

Page 361: ...SPR15 0F115H SEG21 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR16 0F116H SEG22 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR17 0F117H SEG23 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR18 0F118H SEG24 c7 c6 c5 c4 c3 c2 c1 c0 R W DSPR19 0F...

Page 362: ...SEG21 c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR56 0F156H SEG22 c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR57 0F157H SEG23 c15 c14 c13 c12 c11 c10 c9 c8 R W DSPR58 0F158H SEG24 c15 c14 c13 c12 c11 c10 c9 c8 R...

Page 363: ...49C7B Set a frame frequency and a duty by using the display mode register 0 DSPMOD0 When using the programmable display allocation function set the DASN bit of DSPMOD1 register to 1 and set DADM1 bit...

Page 364: ...o 1 16 duty 2 Type 3 Recommended for when using COM0 to COM7 1 1 to 1 8 duty Figure 26 7 Configurations of Display register segment map types Note When the programmable display function is not used DA...

Page 365: ...the DASN bit of DSPMOD1 The programmable display allocation function is available only when 1 1 1 8 duty is selected when using eight COMs or less for display it does not work when 1 9 1 16 duty is se...

Page 366: ...nstance to display bit 6 of display register 23 to common 3 of segment 16 set as follows b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 DS16C3A 0 0 1 0 0 0 1 1 DS16C3B 1 1 0 0F4D0H 0F6D0H Address spe...

Page 367: ...e common output waveforms for 1 8 duty and 1 3 bias and for 1 16 duty and 1 4 bias Figure 26 9 1 Common Output Waveforms for 1 8 Duty and 1 3 Bias 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 COM0 COM1 COM2 COM7 V...

Page 368: ...igure 26 9 2 Common Output Waveforms for 1 16 Duty and 1 4 Bias 0 1 2 3 4 5 6 7 COM0 COM1 COM2 COM15 VL4 VL2 VL1 VSS Frame frequency Approx 64Hz 73Hz 85Hz 102Hz 8 9 10 11 14 15 0 1 2 3 8 9 10 11 14 15...

Page 369: ...2 VL3 VL1 VSS VL4 VL2 VL3 VL1 VSS Frame frequency Approx 64Hz 73Hz 85Hz 102Hz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 SEGn VL4 VL2 VL3 VL1 VSS 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 S...

Page 370: ...0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGn VL2 VL1 VSS VL3 VL4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 SEGn VL2 VL1 VSS VL3 VL4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0...

Page 371: ...Chapter 27 Battery Level Detector...

Page 372: ...Threshold voltages One out of the 16 levels can be selected Accuracy 2 Typ Temperature deviation 0 1 C 27 1 2 Configuration BLD consists of the comparator and threshold voltage select circuits Figure...

Page 373: ...tector 27 2 27 2 Description of Registers 27 2 1 List of Registers Address Name Symbol Byte Symbol Word R W Size Initial value 0F0D0H Battery Level Detector control register 0 BLDCON0 BLDCON R W 8 16...

Page 374: ...R to control the Battery Level Detector Description of Bits LD3 LD2 LD1 LD0 bits 3 0 The LD3 LD2 LD1 and LD0 bits are used to select a threshold voltage VCMP of the Battery Level Detector 16 levels of...

Page 375: ...vation ON or deactivation OFF of the Battery Level Detector The Battery Level Detector is activated ON and deactivated OFF by setting the ENBL bit to 1 and 0 respectively ENBL Description 0 Deactivate...

Page 376: ...ws the threshold voltages and the accuracy Table 27 1 Threshold Voltages and Accuracy BLDCON0 Threshold voltage VCMP Accuracy Ta 25 C Temperature deviation LD3 LD2 LD1 LD0 0 0 0 0 1 35 V 2 0 0 1 C 0 0...

Page 377: ...rison When BLDF bit is set to 1 it indicates the power supply voltage is lower than the threshold voltage When BLDF bit is set to 0 it indicates the power supply voltage VDD is higher than the thresho...

Page 378: ...Chapter 28 Power Supply Circuit...

Page 379: ...for LCD VL1 to VL4 see Chapter 26 LCD Driver 28 1 1 Features VRL outputs the operating voltage VDDL of the internal logic program memory RAM etc VRX outputs the operating voltage VDDX for low speed os...

Page 380: ...n of external interrupt VDDX becomes approx 1 2 V Typ and then approx 0 6 V Typ after 4096 low speed oscillation clock XTCLK pulses are counted Figure 28 2 shows the operation waveforms of the power s...

Page 381: ...Chapter 29 On Chip Debug Function...

Page 382: ...or the flash rewrite function after mounting of the board design the board so that the 6 pins VPP VDD VDDL VSS RESET_N and TEST required for connection to the on chip debug emulator can be connected...

Page 383: ...Kbytes 1 word write Write of 1 word 2 bytes Random read Read of input address Table 29 3 shows the conditions and specifications of Flash memory rewrite Table 29 3 Specifications of Flash Memory Rewr...

Page 384: ...Appendixes...

Page 385: ...00H 0F017H Inperrupt permit register 7 IE7 R W 8 00H 0F018H Inperrupt request register 0 IRQ0 R W 8 00H 0F019H Inperrupt request register 1 IRQ1 R W 8 00H 0F01AH Inperrupt request register 2 IRQ2 R W...

Page 386: ...40H 0F0D0H Battery Level Detector control register 0 BLDCON0 BLDCON R W 8 16 00H 0F0D1H Battery Level Detector control register 1 BLDCON1 R W 8 00H 0F0F0H Bias circuit control register BIASCON R W 8...

Page 387: ...W 8 Undefined 0F12BH Display register 2B DSPR2B R W 8 Undefined 0F12CH Display register 2C DSPR2C R W 8 Undefined 0F12DH Display register 2D DSPR2D R W 8 Undefined 0F12EH Display register 2E DSPR2E R...

Page 388: ...W 8 Undefined 0F15DH Display register 5D DSPR5D R W 8 Undefined 0F15EH Display register 5E DSPR5E R W 8 Undefined 0F15FH Display register 5F DSPR5F R W 8 Undefined 0F160H Display register 60 DSPR60 R...

Page 389: ...e buffer H SIO0BUFH R W 8 00H 0F282H Serial port 0 control register SIO0CON R W 8 00H 0F284H Serial port 0 mode register 0 SIO0MOD0 SIO0MOD R W 8 16 00H 0F285H Serial port 0 mode register 1 SIO0MOD1 R...

Page 390: ...Display allocation register A DS15C0A R W 8 Undefined 0F410H Display allocation register A DS16C0A R W 8 Undefined 0F411H Display allocation register A DS17C0A R W 8 Undefined 0F412H Display allocatio...

Page 391: ...allocation register A DS0C1A R W 8 Undefined 0F441H Display allocation register A DS1C1A R W 8 Undefined 0F442H Display allocation register A DS2C1A R W 8 Undefined 0F443H Display allocation register...

Page 392: ...allocation register A DS50C1A R W 8 Undefined 0F473H Display allocation register A DS51C1A R W 8 Undefined 0F474H Display allocation register A DS52C1A R W 8 Undefined 0F475H Display allocation regis...

Page 393: ...cation register A DS36C2A R W 8 Undefined 0F4A5H Display allocation register A DS37C2A R W 8 Undefined 0F4A6H Display allocation register A DS38C2A R W 8 Undefined 0F4A7H Display allocation register A...

Page 394: ...on register A DS22C3A R W 8 Undefined 0F4D7H Display allocation register A DS23C3A R W 8 Undefined 0F4D8H Display allocation register A DS24C3A R W 8 Undefined 0F4D9H Display allocation register A DS2...

Page 395: ...tion register A DS8C4A R W 8 Undefined 0F509H Display allocation register A DS9C4A R W 8 Undefined 0F50AH Display allocation register A DS10C4A R W 8 Undefined 0F50BH Display allocation register A DS1...

Page 396: ...y allocation register A DS58C4A R W 8 Undefined 0F53BH Display allocation register A DS59C4A R W 8 Undefined 0F53CH Display allocation register A DS60C4A R W 8 Undefined 0F53DH Display allocation regi...

Page 397: ...allocation register A DS44C5A R W 8 Undefined 0F56DH Display allocation register A DS45C5A R W 8 Undefined 0F56EH Display allocation register A DS46C5A R W 8 Undefined 0F56FH Display allocation regis...

Page 398: ...cation register A DS30C6A R W 8 Undefined 0F59FH Display allocation register A DS31C6A R W 8 Undefined 0F5A0H Display allocation register A DS32C6A R W 8 Undefined 0F5A1H Display allocation register A...

Page 399: ...on register A DS16C7A R W 8 Undefined 0F5D1H Display allocation register A DS17C7A R W 8 Undefined 0F5D2H Display allocation register A DS18C7A R W 8 Undefined 0F5D3H Display allocation register A DS1...

Page 400: ...allocation register B DS2C0B R W 8 Undefined 0F603H Display allocation register B DS3C0B R W 8 Undefined 0F604H Display allocation register B DS4C0B R W 8 Undefined 0F605H Display allocation register...

Page 401: ...y allocation register B DS52C0B R W 8 Undefined 0F635H Display allocation register B DS53C0B R W 8 Undefined 0F636H Display allocation register B DS54C0B R W 8 Undefined 0F637H Display allocation regi...

Page 402: ...location register B DS38C1B R W 8 Undefined 0F667H Display allocation register B DS39C1B R W 8 Undefined 0F668H Display allocation register B DS40C1B R W 8 Undefined 0F669H Display allocation register...

Page 403: ...ion register B DS24C2B R W 8 Undefined 0F699H Display allocation register B DS25C2B R W 8 Undefined 0F69AH Display allocation register B DS26C2B R W 8 Undefined 0F69BH Display allocation register B DS...

Page 404: ...on register B DS10C3B R W 8 Undefined 0F6CBH Display allocation register B DS11C3B R W 8 Undefined 0F6CCH Display allocation register B DS12C3B R W 8 Undefined 0F6CDH Display allocation register B DS1...

Page 405: ...y allocation register B DS60C3B R W 8 Undefined 0F6FDH Display allocation register B DS61C3B R W 8 Undefined 0F6FEH Display allocation register B DS62C3B R W 8 Undefined 0F6FFH Display allocation regi...

Page 406: ...y allocation register B DS46C4B R W 8 Undefined 0F72FH Display allocation register B DS47C4B R W 8 Undefined 0F730H Display allocation register B DS48C4B R W 8 Undefined 0F731H Display allocation regi...

Page 407: ...ocation register B DS32C5B R W 8 Undefined 0F761H Display allocation register B DS33C5B R W 8 Undefined 0F762H Display allocation register B DS34C5B R W 8 Undefined 0F763H Display allocation register...

Page 408: ...on register B DS18C6B R W 8 Undefined 0F793H Display allocation register B DS19C6B R W 8 Undefined 0F794H Display allocation register B DS20C6B R W 8 Undefined 0F795H Display allocation register B DS2...

Page 409: ...location register B DS4C7B R W 8 Undefined 0F7C5H Display allocation register B DS5C7B R W 8 Undefined 0F7C6H Display allocation register B DS6C7B R W 8 Undefined 0F7C7H Display allocation register B...

Page 410: ...ocation register B DS45C7B R W 8 Undefined 0F7EEH Display allocation register B DS46C7B R W 8 Undefined 0F7EFH Display allocation register B DS47C7B R W 8 Undefined 0F7F0H Display allocation register...

Page 411: ...Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM...

Page 412: ...age 4 VDDL Ta 25 C 0 3 to 3 6 V Power supply voltage 5 VDDX Ta 25 C 0 3 to 3 6 V Power supply voltage 6 VL1 Ta 25 C 0 3 to 1 75 V Power supply voltage 7 VL2 Ta 25 C 0 3 to 3 5 V Power supply voltage 8...

Page 413: ...4 1 0 30 F Clock Generation Circuit Operating Conditions VSS 0V Parameter Symbol Condition Rating Unit Min Typ Max Low speed crystal oscillation frequency fXTL 32 768k Hz Recommended equivalent series...

Page 414: ...Operating temperature TOP At erase program 0 to 40 C Operating voltage VDD At erase program 1 2 75 to 3 6 V VDDL At erase program 1 2 5 to 2 75 VPP At erase program 1 7 7 to 8 3 Erase program cycles C...

Page 415: ...e TRC 50 500 s High speed crystal oscillation start time 3 TXTH VDD 1 8 to 3 6V 2 20 ms PLL oscillation start time TPLL VDD 1 8 to 3 6V 1 10 Low speed oscillation stop detect time 1 TSTOP 0 2 3 20 Res...

Page 416: ...21 1 26 1 31 CN4 0 11H 1 23 1 28 1 33 CN4 0 12H 1 25 1 30 1 35 CN4 0 13H 1 27 1 32 1 37 CN4 0 14H 1 1 29 1 34 1 39 CN4 0 15H 1 1 31 1 36 1 41 CN4 0 16H 1 1 33 1 38 1 43 CN4 0 17H 1 1 35 1 40 1 45 CN4...

Page 417: ...5 to 3 6V 0 1 C Supply current 1 6 IDD1 CPU In STOP state Low speed high speed oscillation stopped Ta 25 C 0 15 0 50 A Ta 20 to 70 C 2 50 Ta 40 to 85 C 5 00 Supply current 2 6 IDD2 CPU In HALT state L...

Page 418: ...1 5 1 6 mA Ta 20 to 70 C 2 5 Ta 40 to 85 C 2 5 1 CPU operating rate is 100 No HALT state 2 All SEGs off waveform No LCD panel load 1 3 bias 1 3 duty Frame frequency Approx 64 Hz Bias voltage multiplyi...

Page 419: ...5 C 4 6 A Ta 20 to 70 C 9 Ta 40 to 85 C 10 Supply current 4 IDD4 CPU In 500kHz CR operating state LCD BIAS circuits Operating 2 Ta 25 C 60 75 A Ta 20 to 70 C 95 Ta 40 to 85 C 100 Supply current 5 IDD5...

Page 420: ...1 3 to 3 6V VDD 0 3 IOH1 0 03mA VDD 1 1 to 3 6V VDD 0 3 VOL2 IOL2 5mA VDD 1 8 to 3 6V 0 5 Output voltage 3 P40 P41 VOL3 IOL3 3mA VDD 2 0 to 3 6V when I 2 C mode is selected 0 4 Output voltage 4 COM0...

Page 421: ...ate 1 1 ML610Q421 ML610421 only 2 ML610Q422 only DC Characteristics 6 6 VDD 1 1 to 3 6V AVDD 2 2 to 3 6V VSS AVSS 0V Ta 20 to 70 C Ta 40 to 85 C for P Version unless otherwise specified 6 6 Parameter...

Page 422: ...c circuit to determine the specified measuring conditions 2 Measured at the specified output pins 2 1 XT0 XT1 P10 OSC0 P11 OSC1 32 768kHz crystal 4 096MHz crystal CGH CDH A VDD AVDDVREFVDDL VDDX CL1 C...

Page 423: ...pins 3 Measured at the specified output pins 3 Input pins VDD AVDD VREF VDDL VDDX VL1 VL2 VL3 VL4 VSSAVSS VIH VIL Output pins 1 Input logic circuit to determine the specified measuring conditions 1 W...

Page 424: ...s AC Characteristics UART VDD 1 3 to 3 6V AVDD 2 2 to 3 6V VSS AVSS 0V Ta 20 to 70 C Ta 40 to 85 C for P Version unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max Transmit...

Page 425: ...e 2 VDD 1 3 to 3 6V 500 ns When high speed oscillation is active 3 VDD 1 8 to 3 6V 240 SOUT output delay time master mode tSD When RC oscillation is active 2 VDD 1 3 to 3 6V 500 ns When high speed osc...

Page 426: ...DAT 0 25 s SDA setup time stop condition tSU STO 4 0 s Bus free time tBUF 4 7 s AC Characteristics I2 C Bus Interface Fast Mode 400kHz VDD 1 8 to 3 6V AVDD 2 2 to 3 6V VSS AVSS 0V Ta 20 to 70 C Ta 40...

Page 427: ...ency ratio 1 VDD 3 0V Kf1 RT0 RT0 1 RT1 1kHz 8 006 8 210 8 416 Kf2 RT0 RT0 1 RT1 10kHz 0 99 1 1 01 Kf3 RT0 RT0 1 RT1 100kHz 0 100 0 108 0 115 1 Kfx is the ratio of the oscillation frequency by the sen...

Page 428: ...n Type A D Converter VDD 1 8 to 3 6V AVDD 2 2 to 3 6V VSS AVSS 0V Ta 20 to 70 C Ta 40 to 85 C for P Version unless otherwise specified Parameter Symbol Condition Rating Unit Min Typ Max Resolution n 1...

Page 429: ...ircuit see Section 6 3 1 Low Speed Clock RESET_N XT0 XT1 32 768KHz Xtal CGL CDL C4 C3 P30 IN0 C34 LCD C2 C1 C12 VDDX VL1 VL2 VL3 VL4 VDD CL1 C1 CL0 P22 MD0 CS0 RS0 RT0 P31 CS0 P32 RS0 P33 RT0 P34 RCT0...

Page 430: ...clock generation circuit see Section 6 3 1 Low Speed Clock RESET_N XT0 XT1 32 768KHz Xtal CGL CDL C4 C3 P30 IN0 C34 LCD C2 C1 C12 VDDX VL1 VL2 VL3 VL4 VDD CL1 CL0 P22 MD0 CS0 RS0 RT0 P31 CS0 P32 RS0 P...

Page 431: ...flag is provided that indicates the occurrence of reset by the RESET_N pin Refer to section 3 2 2 in the user s manual BRK instruction reset In system reset by the BRK instruction no special function...

Page 432: ...er s manual A high speed crystal ceramic oscillation or an external clock input mode does not require specifying the 2 nd function for the port 1 Refer to Section 18 3 2 Chapter 7 TBC Time Base Counte...

Page 433: ...ort A Chapter 23 Melody Buzzer Enabling the LSCLK x 2 Set ENMLT bit of FCON1 register to 1 to enable the low speed double clock LSCLK x 2 before stating the melody or buzzer outputs Port 2 nd Function...

Page 434: ...d Please select the threshold voltage when the BLD circuit is OFF Chapter 28 Power circuit External capacitor CL0 1uF connected to VDDL pin Cx 0 1uF connected to VDDX pin Chapter 29 On chip debug ML61...

Page 435: ...Revision History...

Page 436: ...C 5 1 conditions are corrected FEUL610Q421 04 Dec 3 2010 Add to B version FEUL610Q421 05 Jun 1 2011 Add to ML610421 ML610422 1 7 Block diagram of ML610421 is added 1 8 Block diagram of ML610422 is ad...

Page 437: ...1 8 Delete ML610421 Mask ROM TQFP Package Version 1 3 1 4 1 3 1 4 Delete Low speed clock oscillation stop detection reset un carrying version B version 1 4 1 4 Change from Shipment to Product name Su...

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