LAPIS Semiconductor ML610421, User Manual, Page: 52 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 3 Reset Function
3 – 3
3.3 Description of Operation
3.3.1 Operation of System Reset Mode
System reset has the highest priority among all the processings and any other processing being executed up to then is
cancelled.
The system reset mode is set by any of the following causes.
•
Reset by the RESET_N pin
•
Reset by power-on detection
•
Reset by low-speed oscillation stop detection
•
Reset by 2
nd
watchdog timer (WDT) overflow
•
Software reset by the BRK instruction (only the CPU is reset)
In system reset mode, the following processing is performed.
(1) The power circuit is initialized, but not initialized by the reset by the BRK instruction execution. For the details of
the power circuit, refer to Chapter 28, “Power Circuit”.
(2) All the special function registers (SFRs) whose initial value is not undefined are initialized. However, the
initialization is not performed by software reset due to execution of the BRK instruction. See Appendix A
“Registers” for the initial values of the SFRs.
(3) CPU is initialized.
•
All the registers in CPU are initialized.
•
The contents of addresses 0000H and 0001H in the program memory are set to the stack pointer (SP).
•
The contents of addresses 0002H and 0003H in the program memory are set to the program counter (PC).
However, when the interrupt level (ELEEVL) of the program status word (PSW) at reset by the BRK instruction
is 1 or lower, the contents of addresses 0004H and 0005H of the program memory are set in the program counter
(PC). For the BRK instruction, see “nX-U8/100 Core Instruction Manual”.
Note:
In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not
initialized and are undefined. Initialize them by software.
In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is
initialized either. Therefore initialize such an SFR by software.