LAPIS Semiconductor ML610421, User Manual, Page: 194 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 13 Synchronous Serial Port
13 – 14
13.4.4 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode”
Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0
register) to “0”, for specifying the SSIO as the secondary function of P46, P45 and P44. They are the same setting as
those in the case of master mode.
Reg. name P4MOD1 register (Address: 0F225H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1
Data * 1 1 1 * * * :
Reg. name P4MOD0 register (Address: 0F224H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0
Data * 0 0 0 * * * *
Set P46C1 bit(bit6 of P4CON1 register) to “1”, set P46C0 bit(bit6 of P4CON0 register) to “1”, and set P46DIR
bit(bit6 of P4DIR register) to “0”, for specifying the P46 as CMOS output.
Set P45DIR-P44DIR bits(bit5-4 of P4DIR register) to “1” for specifying the P45 and P44 as input pins.
Data setting to P45C1 bit, P44C1 bit, P45C0 bit and P44C0 bit, depend on the application circuit connected to P45 and
P44.
Reg. name P4CON1 register (Address: 0F223H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1
Data * 1 $ $ * * * *
Reg. name P4CON0 register (Address: 0F222H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0
Data * 1 $ $ * * * *
Reg. name P4DIR register (Address: 0F221H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR
Data * 0 1 1 * * * *
Data of P46D-P44D bits (bit6-4 of P4D register) do not affect to the SSIO function, so don’t care the data for the
function.
Reg. name P4D register (Address: 0F220H)
Bit 7 6 5 4 3 2 1 0
Bit name
P47D P46D P45D P44D P43D P42D P41D P40D
Data * ** ** ** * * * *
- : Bit not related to the SSIO(using P46, P45, and P44) function
** : Don’t care the data
$ : Arbitrarily