LAPIS Semiconductor ML610421, User Manual, Page: 84 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 5 Interrupts (INTs)
5 – 15
5.2.14 Interrupt Request Register 5 (IRQ5)
Address: 0F01DH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
IRQ5

QTM3 QTM2
    
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ5 request flag is set to “1” regardless of the IE5 and MIE values when an interrupt is generated. In this case,
an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “1” and the
master interrupt enable flag (MIE) is set to “1”.
By setting the IRQ5 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ5 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
•
QTM2 (bit 5)
QTM2 is the request flag for the timer 2 interrupt (TM2INT).
QTM2 Description
0 No request (initial value)
1 Request
•
QTM3 (bit 6)
QTM3 is the request flag for the timer 3 interrupt (TM3INT).
QTM3 Description
0 No request (initial value)
1 Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ5) or to the interrupt enable
register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed.