LAPIS Semiconductor ML610421, User Manual, Page: 334 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 25 Successive Approximation Type A/D Converter
25 – 7
25.2.7 SA-ADC Control Register 1 (SADCON1)
Address: 0F2F1H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
SADCON1
      
SARUN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC.
[Description of Bits]
•
SARUN (bit 0)
SARUN Description
0 Stops conversion. (Initial value)
1 Starts conversion.
The SARUN bit is used to start or stop SA-ADC conversion. Setting this bit to “1” starts A/D conversion and setting it
to “0” stops A/D conversion.
When SALP of SADCON0 is “0” and then A/D conversion on the channel with the largest channel number among the
selected ones is terminated, the SARUN bit is automatically set to “0”.
Notes:
Use the SA-ADC with high-speed clock oscillation (HSCLK) enabled in the frequency control register (FCON0).
The SA-ADC is available only when V
DD
= 1.8 to 3.6 V and HSCLK is in the ranges of 3.75kHz to 625kHz and of
1.5MHz to 4.2 MHz.
Do not start A/D conversion in the state in which bits 1 (SACH1) and 0 (SACH0) of SA-ADC mode register 0 are “0”
and “0” respectively. When A/D conversion is started in this state, A/D conversion is not done while the A/D converter
is activated. Therefore, the SA-ADC result register is not updated, the A/D conversion termination interrupt is not
generated, A/D conversion is not terminated automatically, and SARUN remains “1”.