LAPIS Semiconductor ML610421, User Manual, Page: 87 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 5 Interrupts (INTs)
5 – 18
5.3 Description of Operation
With the exception of the watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT), interrupt
enable/disable for 20 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable
registers (IE1 to 7). WDTINT and NMIINT are non-maskable interrupts.
When the interrupt conditions are satisfied, the CPU calls a branching destination address from the vector table
determined for each interrupt source and the interrupt shift cycle starts to branch to the interrupt processing routine.
Table 5-1 lists the interrupt sources.
Table 5-1 Interrupt Sources
Priority Interrupt source Symbol Vector table address
1 Watchdog timer interrupt WDTINT 0008H
2 NMI interrupt NMINT 000AH
3 P00 interrupt P00INT 0010H
4 P01 interrupt P01INT 0012H
5 P02 interrupt P02INT 0014H
6 P03 interrupt P03INT 0016H
7 Synchronous serial port 0 interrupt SIO0INT 0020H
8
Successive approximation type A/D
converter interrupt
SADINT 0024H
9 I
2
C bus 0 interrupt I2C0INT 002EH
10 Timer 0 interrupt TM0INT 0030H
11 Timer 1 interrupt TM1INT 0032H
12 UART 0 interrupt UA0INT 0040H
13 Melody 0 interrupt MD0INT 0044H
14
RC oscillation type A/D converter
interrupt
RADINT 004AH
15 Timer 2 interrupt TM2INT 0058H
16 Timer 3 interrupt TM3INT 005AH
17 PWM0 interrupt PW0INT 0060H
18 1 kHz timer interrupt T1KINT 0068H
19 TBC128Hz interrupt T128HINT 006AH
20 TBC32Hz interrupt T32HINT 006EH
21 TBC16Hz interrupt T16HINT 0070H
22 TBC2Hz interrupt T2HINT 0076H
Note:
- When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and
processing of low-priority interrupts is pending.
-
Please define vector tables for all unused interrupts for fail safe.