LAPIS Semiconductor ML610421, User Manual, Page: 94 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 6 Clock Generation Circuit
6 – 1
6. Clock Generation Circuit
6.1 Overview
The clock generation circuit generates and provides a low-speed clock (LSCLK), 2
×
low-speed clock (LSCLK2), a
high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK,
LSCLK
×
2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU,
and OUTCLK is a clock that is output from a port.
For the OUTCLK output port, see Chapter 19, “Port 2”.
Additionally, for the STOP mode described in this chapter, see Chapter 4, “MCU Control Function”, and for BLD, see
Chapter 27, “Battery Level Detection Circuit”.
6.1.1 Features
•
Low-speed clock: 32.768 kHz crystal oscillation mode
−
Capable of generating LSCLK
×
2 (64 kHz) to be used for some peripherals.
•
High-speed clock: Software selection
−
500 kHz RC oscillation mode
−
Crytal/ceramic oscillation mode
−
Built-in PLL oscillation mode
−
External clock input mode
6.1.2 Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
Figure 6-1 Configuration of Clock Generation Circuit
Note:
This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power-on
or a system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required one.
Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied.
XT0
XT1
High-speed
clock generation
circuit
P10/OSC0
P11/OSC1
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
System clock
(SYSCLK)
MP
X
FCON0, FCON1
Data bus
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
High-speed output clock
(OUTCLK)
OSCLK
Low-speed
clock generation
circuit
2
×
low-speed clock
(LSCLK
×
2)