LAPIS Semiconductor ML610421, User Manual, Page: 352 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 26 LCD Drivers
26 – 14
26.2.5 Display Mode Register 1 (DSPMOD1)
Address: 0F0F3H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
DSPMOD1
    
DASN DADM1 DADM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
DSPMOD1 is a special register (SFR) to control the display mode of the LCD drivers.
Use DSPMOD1 to select a type of display register segment map and determine to use or unuse the programmable display
allocation function (display allocation RAM).
[Description of Bits]
•
DADM1, DADM0 (bits 1-0)
DADM1 and DADM0 are used to select a type of display register segment map. Two types are available; type 2, and
type 3 (type 1 is not available on ML610Q421/ML610Q422/ML610421) . See section 26.2.9 and section 26.3.2.
DADM1 DADM0 Description
0 * Display register segment map type 2 (initial value)
1 * Display register segment map type 3
•
DASN (bit 2)
The DASN bit is used to control the operation of the display allocation function.
Setting the DASN bit to “1” enables the display allocation function.
DASN Description
0 Not use Programmable display allocation (initial value)
1 Use Programmable display allocation
Note:
When using the programmable display allocation, select type 3 for the display register segment map. Oki semiconductor
LCD Tool only generates table data can be used for the type 3.