LAPIS Semiconductor ML610421, User Manual, Page: 317 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 24 RC Oscillation Type A/D Converter
24 – 13
(2) Operation in Counter B reference mode
Figure 24-7 shows the operation timing in Counter B reference mode.
Following is an example of operation procedure in Counter B reference mode:

Preset to Counter B (RADCB2–0) the value obtained by subtracting the count value “nB1” from the maximum
value + 1 (1000000H). The product of the count value “nB1” and the RCCLKclock period indicates the gate
time.

Preset “000000H” to Counter A (RADCA2–0).

Set the OM3–OM0 bits of RADMOD to desired oscillation mode (see Table 24-1).

Set the RADI bit of RADMOD to “1” to specify generating of an interrupt request signal by Counter B overflow.

Set the RARUN bit of RADCON to “1” to start A/D conversion.
When the RARUN bit is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set
to”1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC oscillator clock (RCCLK).
When Counter B overflows, the RARUN bit is automatically reset (

) and conversion operation terminates. At the
same time, an RC-ADC interrupt request (RADINT) occurs. (

)
When the RCON signal is set to “1”, Counter A starts counting of the base clock (BSCLK). When the RARUN bit is
reset due to overflow of Counter B, Counter A stops counting.
The final count “nA1” of Counter A is the CLK count value during the gate time “nB1

t
RCCLK
” and is expressed by the
following expression:
nA1
≅
nB1•
t
RCCLK ∝
1
t
BSCLK
f
RCCLK
That is, “nA1” is a value inversely proportional to the RC oscillation frequency f
RCCLK
.