LAPIS Semiconductor ML610421, User Manual, Page: 316 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 24 RC Oscillation Type A/D Converter
24 – 12
Counter A starts counting of the base clock (BSCLK) when RARUN is set to “1” and the RCON signal (signal
synchronized with the fall of the base clock) is set to “1”. When Counter A overflows, the RARUN bit is
automatically reset to “0” (

) and counting is terminated. At the same time, an RC-ADC interrupt request (RADIN)
occurs (

).
When the RCON signal is set to “1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC
oscillator clock (RCCLK). When the RARUN bit is reset to “0” due to overflow of Counter A, RC oscillation stops
and Counter B stops counting.
The final count value “nB0” of Counter B is the RCCLK count value during the gate time “nA0

t
BSCLK
” and is
expressed by the following expression:
nB0
≅
nA0•
t
BSCLK
∝
f
RCCLK
t
RCCLK
where t
BSCLK
indicates the BSCLK period and t
RCCLK
the RCCLK period. That is, “nB0” is a value proportional to the
RC oscillation frequency f
RCCLK
.
(1000000H – nA0)
(+1) (+2) (+3) 0FFFFFCH
000000H
t
BSCLK

Overflow
Gate time
nA0·t
BSCLK

000000H 000001H 000002H nB0 – 2 nB0 – 1 nB0

nB0·t
RCCLK

(Interrupt request)
t
RCCLK
RARUN
BSCLK
RCON
Counter A
CR oscillator circuit
Input waveform
IN0/IN1
RCCLK
Counter B
RADINT
nA0: Reference count value
nB0: Measurement count value

0FFFFFDH 0FFFFFEH 0FFFFFFH
Figure 24-6 Operation Timing in Counter A Reference Mode