LAPIS Semiconductor ML610421, User Manual, Page: 196 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 14 UART
14 – 1
14. UART
14.1 Overview
This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchrnous serial
interface.
For the input clock, see Chapter 6, “Clock Generation Circuit”.
The use of UART requires setting of the secondary functions of Port 4. For setting of the secondary functions of Port
4, see Chapter 21, “Port 4”.
14.1.1 Features
•
5-bit/6-bit/7-bit/8-bit data length selectable
•
Odd parity, even parity, or no parity selectable
•
1 stop bit or 2 stop bits selectable
•
Provided with parity error flag, overrun error flag, framing error flag, and transmit buffer status flag.
•
Positive logic or negative logic selectable as communication logic
•
LSB first or MSB first slectable as a communication direction
•
Communication speed: Settable within the range of 200bps to 115200bps
•
Built-in baud rate generator
14.1.2 Configuration
Figure 14-1 shows the configuration of the UART.
UA0BUF: UART0 transmit/receive buffer
UA0BRTH, L: UART0 baud rate registers H, L
UA0CON: UART0 control register
UA0MOD0, 1: UART0 mode registers 0, 1
UA0STAT: UART0 status register
Figure 14-1 Configuration of UART
14.1.3 List of Pins
Pin name I/O Description
P02/RXD0 I
UART0 data input pin
Used for the secondary function of the P02 pin.
P42/RXD0 I
UART0 data input pin
Used for the secondary function of the P42 pin.
P43/TXD0 O
UART0 data output pin
Used for the secondary function of the P43 pin.
UA0BUF
Shift Register
UA0INT
Band Rate
Generator
UA0CON
UA0MOD0, 1
UA0STAT
UART
Controller
P43/TXD0
LSCLK
HSCLK
Data bus
UA0BRTH, L
LSCLK
×
2
P42/RXD0
P02/RXD0