LAPIS Semiconductor ML610421, User Manual, Page: 111 / 437

ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 7 Time Base Counter
7 – 1
7. Time Base Counter
7.1 Overview
This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base
clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically.
For input clocks, see Chapter 6, “Clock Generation Circuit”. For interrupt permission, interrupt request flags, etc.,
described in this chapter, see Chapter 5, “Interrupts”.
7.1.1 Features
•
LTBC generates T32KHZ to T1HZ signals by dividing the low-speed clock (LSCLK) frequency.
•
LTBC allows frequency adjustment (Adjustment range: Approx.
−
488ppm to +488ppm. Adjustment accuracy:
Approx. 0.48ppm) by using the low-speed time base counter frequency adjustment registers (LTBADJH and
LTBADJL).
•
HTBC generates HTB1 to HTB32 signals by dividing the high-speed clock (HSCLK) frequency.
•
Capable of generating 128Hz , 32Hz , 16Hz , and 2Hz interrupts.
7.1.2 Configuration
Figure 7-1 and Figure 7-2 show the configuration of a low-speed time base counter and a high-speed time base counter,
respectively.
LTBR : Low-speed time base counter register
LTBADJL : Low-speed time base counter frequency adjust register
LTBADJH : Low-speed time base counter frequency adjust register
Figure 7-1 Configuration of Low-Speed Time Base Counter (LTBC)
LSCLK
(32.768 kHz)
7-bit Counter
R
LTBR
8-bit Counter
R
RESET
(Internal signal)
LTBR Write
LTBADJL
LTBDJH
8
Data bus
T2HZ
T4HZ
T8HZ
T16HZ
T32HZ
T64HZ
T128HZ
T256HZ
T512HZ
T1KHZ
T2KHZ
T4KHZ
T8KHZ
T16KHZ
T32KHZ
T1HZ
8