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External clock mode 2
After polarity selection, frequency division and filtering, the signal from external
trigger interface (ETR) is connected to slave mode controller through trigger
input selector to control the work of counter.
Internal trigger input
The timer is set to work in slave mode, and the clock source is the output signal
of other timers. At this time, the clock source has no filtering, and the
synchronization or cascading between timers can be realized. The master mode
timer can reset, start, stop or provide clock for the slave mode timer.
Timebase unit
The time base unit in the advanced timer contains four registers
Counter register (CNT) 16 bits
Auto reload register (AUTORLD) 16 bits
Prescaler register (PSC) 16 bits
Repetition count register (REPCNT) 8 bits
Counter CNT
There are three counting modes for the counter in the advanced timer
Count-up mode
Count-down mode
Center-aligned mode
Count-up mode
Set to the count-up mode by CNTDIR bit of configuration control register
(TMRx_CTRL1).
When the counter is in count-up mode, the counter will count up from 0; every
time a pulse is generated, the counter will increase by 1 and when the value of
the counter (TMRx_CNT) is equal to the value of the auto reload
(TMRx_AUTORLD), the counter will start to count again from 0, a count-up
overrun event will be generated, and the value of the auto reload
(TMRx_AUTORLD) is written in advance.
When the counter overruns, an update event will be generated. At this time, the
repeat count shadow register, the auto reload shadow register and the prescaler
buffer will be updated. The update event can be disabled by UD bit of
configuration control register TMRx_CTRL1.
The figure below is Timing Diagram when Division Factor is 1 or 2 in Count-up
Mode
