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Clock Tree
Figure 4 APM32F030x4x6x8xC Clock Tree
Clock output
PLLCLK
HSICLK
HSICLK14
HSECLK
SYSCLK
LSICLK
LSECLK
HSICLK
8MHz
HSECLK OSC
4-32MHz
HSICLK14
RC
14MHz
LSECLK OSC
32.768kHz
LSICLK
40kHz
/1,2
16
PLLMUL
×2,×3
×16
/1,2
/512
/8
/1,/2,/
4,/8,/1
6
APB
peripheral
TMR1/3/6/1
4/15/16/17
ADC
System Timer
AHB/Core/
Memory//DMA
I2C1/2
Flash programming
interface
SYSCLK
HCLK
APB_CLK
×1,×2
HSICLK
RTC
/32
HSECLK
LSECLK
LSICLK
IWDT
LSECLK
LSICLK
LSICLK
HSICLK14
MCO
HSICLK
OSC_OUT
OSC_IN
OSC32_OUT
OSC32_IN
HSICLK
PLLCLK
HSECLK
USART1
SYSCLK
HSICLK
LSECLK
/2
AHBPSC
APBPSC
SW
CSS
HSICLK
/2,/4
Note:
（
1
）
HCLK means AHB clock.
（
2
）
PCLK is clock signal of the peripheral connected to APB.
（
3
）
FCLK is running clock of Arm
®
Cortex
®
-M0+.
（
4
）
The frequency of AHB, APB2 (high-speed APB) and APB1 (low-speed APB) domains can be
configured through multiple prescalers
（
5
）
When needing to run the peripheral connected to AHB and APB, it is required to turn on the
corresponding enable end to make the peripheral get the clock signal.
（
6
）
Frequency assignment of all TMRxCLK (timer clocks) is automatically set by the hardware
according to the following two situations:
If the corresponding APB prescaler factor is 1, the clock frequency of the timer is the
same as that of the APB bus.
Otherwise, the clock frequency of the timer will be set to twice the frequency of the APB
bus connected to it.
（
7
）
Moreover, the frequency of TMRx (x=1, 3, 6, 14, 15, 16, 17) clock signal is divided through
APB.
