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Reset value: 0x0000
Field
Name
R/W
Description
4:0
DBADDR R/W
DMA Base Address Setup
These bits define the base address of DMA in continuous mode (when
reading or writing TMR15_DMA register), and DBADDR is defined as the
offset from the address of TMR15_CTRL1 register:
00000
：
TMR15_CTRL1
00001
：
TMR15_CTRL2
00010
：
TMR15_SMCTRL
…….
7:5
Reserved
12:8
DBLEN
R/W
DMA Burst Transfer Length Setup
These bits define the transfer length and transfer times of DMA in
continuous mode. The data transferred can be 16 bits and 8 bits.
When reading/writing TMRx_DMADDR register, the timer will conduct a
continuous transmission;
00000: Transmission for 1 time
00001: Transmission for 2 times
00010: Transmission for 3 times
……
10001: Transmission for 18 times
The transmission address formula is as follows:
Transmission address=TMRx_CTRL1 address (slave address)
+DMA index; DMA index=DBLEN
For example: DBLEN=7, DBADDR=TMR1_CTRL1 (slave address) means
the address of the data to be transmitted, while the a7 of
TMRx_CTRL1 means the address of the data to be written/read,
Data transmission will occur to: TMRx_CTRL1 a seven registers
starting from DBADDR.
The data transmission will change according to different DMA data length:
When the transmission data is set to 16 bits, the data will be transmitted to
seven registers
When the transmission data is set to 8 bits, the data of the first register is
the MSB bit of the first data, the data of the second register is the LSB bit of
the first data, and the data will still be transmitted to seven registers.
15:13
Reserved
DMA address register of continuous mode (TMR15_DMADDR)
Offset address: 0x4C
Reset value: 0x0000
Field
Name
R/W
Description
15:0
DMADDR R/W
DMA Register for Burst Transfer
Read or write operation access of TMR15_DMADDR register may lead to
access operation of the register in the following address:
TMR15_CTRL1 a (DMA index) ×4
Wherein:
"TMR15_CTRL1 address" is the address of control register 1
(TMR15_CTRL1);
"DBADDR" is the base address defined in TMR15_DCTRL register;
"DMA index" is the offset automatically controlled by DMA, and it depends
on DBLEN defined in TMR15_DCTRL register.
