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Table 78 Four Modes of SPI
SPI mode
CPHA
CPOL
Sampling moment
Idle SCK clock
0
0
0
Odd edge
Low level
1
0
1
Odd edge
High level
2
1
0
Even edge
Low level
3
1
1
Even edge
High level
Note:
（
1
）
To change CPOL and CPHA bits, SPI must be cleared and disabled through SPIEN bit
（
2
）
When SCK is in idle state, if CPOL=1, pull up SCK; if CPOL=0, pull up SCK.
23.4.2.2
Data frame format
Select LSB or MSB first by configuring LSBSEL bit of SPI_CTRL1 register.
Select the data word length by configuring DSCFG bit of SPI_CTRL2 register; no
matter which data word length is selected; it must be aligned with FRTCFG when
read access is conducted to FIFO. When accessing SPI_DATA register, the data
frames are always right aligned. In the process of communication, only the bits
within the data word length range will be output with the clock.
NSS mode
Software NSS mode: Select to enable or disable this mode by configuring SSEN
bit of SPI_CTRL1 register, and the internal NSS signal level is driven by ISSEL
bit of SPI_CTRL1 register.
Hardware NSS mode:
Turn on NSS output: When SPI is in master mode, enable SSOEN bit,
NSS pin will be pulled to low level and SPI will automatically enter the
slave mode.
Turn off NSS output: Operation is allowed in multiple master
environments.
SPI mode
23.4.4.1
Initialization of SPI master mode
In master mode, serial clock is generated on SCK pin.
Configure master mode
Configure MSMCFG=1 in SPI_CTRL1 register, and set it as master
mode
Select the serial clock baud rate by configuring BRSEL bit in
SPI_CTRL1 register
Select the polarity and phase by configuring CPOL and CPHA bits in
SPI_CTRL1 register
