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RTC domain control register (RCM_RTCCTRL)
Offset address: 0x20
Reset value: 0x0000 0018, which can be reset effectively only by RTC domain
Access: Access in the form of word, half word and byte, with 0 to three wait
cycles
When the register is accessed continuously, the waiting state will be inserted.
Note: Only when BPWEN bit in PMU_CTRL is set to 1, can LSEEN, LSEBCFG,
RTCSRCSEL and RTCCLKEN be changed.
Field
Name
R/W
Description
0
LSEEN
R/W
Low-Speed External Oscillator Enable
0: Disable
1: Enable
1
LSERDYFLG
R
Low-Speed External Clock Ready Flag
When LSECLK is stable, this bit is set to 1 by hardware, and when it is
unstable, it is cleared by hardware.
0: Not ready
1. Ready
2
LSEBCFG
R/W
Low-Speed External Clock Bypass Mode Configure
Bypass mode refers to the mode in which external clock is used as the
LSECLK clock source; otherwise the resonator is used as the LSECLK
clock source.
0: Non-bypass mode
1: Bypass mode
4:3
LSEDRVCFG
R/W
LSE Oscillator Drive Capability Configure
This bit is set or cleared by software; set the driving capability of
LSECLK oscillator (crystal mode is not bypassed). When the RTC
domain is reset, this bit is restored to the default value.
00: Weak
01: Medium and low
10: Medium and high
11: Strong
7:5
Reserved
9:8
RTCSRCSEL R/W
RTC Clock Source Select
First set the RTCRST bit to reset the RTC domain, and then select the
RTC clock source. It is impossible to directly configure the register to
modify.
00: No clock
01: LSECLK is used as RTC clock
10: LSICLK is used as RTC clock
11: HSECLK is used as RTC clock after 32 divided frequency
14:10
Reserved
15
RTCCLKEN
R/W
RTC Clock Enable
0: Disable
1: Enable
