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Field
Name
R/W
Description
When STS_PEF=1 or STS_WPEF=1, set this bit to generate an interrupt.
11
Reserved
12
OCIE
R/W
Operation Complete Interrupt Enable
0: Operation completion interrupt is disabled
1: Operation completion interrupt is enabled
When STS_OCF=1, set this bit to generate an interrupt.
13
OBLOAD
R/W
Force Option Byte Load
When this bit is set to 1, force to reload the option byte to generate system
reset.
0: Idle
1: Force to load
31:14
Reserved
Address register (FMC_ADDR)
Offset address: 0x14
Reset value: 0x0000 0000
The register is changed to currently/finally used address by hardware; in page
erasing, the register needs to be configured by software.
Field
Name
R/W
Description
31:0
ADDR
W
Flash Address
In programming operation, the bit is written to the address to be programmed;
in page erasing, this bit is written to the page to be erased.
Option bye control/state register (FMC_OBCS)
Offset address: 0x1C
Reset value: 0xXXXX XX0X
The reset value of the register is related to the value in the written option byte;
the reset value of OBE bit is related to the result whether the value of the loaded
option byte is consistent with its reverse code.
Field
Name
R/W
Description
0
OBE
R
Option Byte Error
1: The loaded option byte does not match its complementary code. The
option byte and its complementary code are forced to write to 0xFF
2:1
READPROT
R
Indicate which level of read protection was enabled.
If bit1 is set to 1, it is level 1. If bit2 is set to 1, it is level 2.
00: Level 0
01: Level 1
1X: Level 2
7:3
Reserved
8
WDTSEL
R
Watchdog Select
0: Hardware watchdog
1: Software watchdog
