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disabled); MSMCFG is cleared and the device is forced to enter the slave mode.
Operation of clearing the MEFLG flag bit: When MEFLG flag bit is set to 1, it is
required to read or write SPI_STS register, and then write to SPI_CTRL1
register.
When MEFLG flag bit is 1, it is not allowed to set SPIEN and MSMCFG bits.
Overrun error OVRFLG
An overrun error will be generated when the following events occur
When RXBNEFLG flag bit is still 1 after the master device has
transmitted data
When the space in RXFIFO cannot store the data to be received when
receiving data
When the software or DMA cannot read the data in RXFIFO in time
When CRC is only enabled in receiving mode, RXFIFO is not available
and the receive buffer is limited to the single data frame buffer
When an overrun error occurs: OVRFLG bit is set to 1; if ERRIEN bit is also set,
an interrupt will be generated.
After an overrun error occurs, the data in the receiving buffer are not the data
transmitted by the master device, and by reading SPI_DATA value, the data are
the data not read before, and the subsequent data will be discarded.
OVRFLG flag can be cleared by reading SPI_DATA register and SPI_STS
register according to the sequence.
CRC error flag bit CRCEFLG
Enable CRC operation by setting CRCEN bit of SPI_CTRL1 register, and CRC
error flag can check whether the received data are valid.
When the value transmitted by SPI_TXCRC register does not match the value in
SPI_RXCRC register, a CRC error will be generated, and CRCEFLG flag bit in
SPI_STS register will be set to 1.
CRCEFLG can be cleared by writing 0 to CRCEFLG bit of SPI_STS register.
TI mode frame format error (FREFLG)
Under the slave device and in accordance with TI mode protocol, when a pulse
appears in NSS during data communication, a TI mode frame format error will be
caused. When TI mode frame format error occurs, FREFLG flag bit of SPI_STS
register will be set to 1, SPI will not be disabled, NSS pulse will be ignored, and
SPI will wait for the next NSS pulse before retransmission. As the error detection
may cause the loss of two data bytes, the data may have been damaged.
FREFLG flag can be cleared by reading SPI_STS register. If ERRIEN bit is set,
an interrupt will be generated when NSS error occurs. At this time, SPI is
disabled because the consistency of data cannot be guaranteed. When SPI is
enabled again, the master server needs to be reinitialized.
Table 80 SPI Interrupt Request
Interrupt flag
Interrupt event
Enable
control bit
Clearing method
TXBEFLG
Transmit buffer empty flag
TXBEIEN
Write SPI_DATA register
RXBNEFLG
Receive buffer non-empty flag
RXBNEIEN
Read SPI_DATA register
