www.geehy.com Page 255
Synchronous Mode
The synchronous mode supports full duplex synchronous serial communication
in master mode, and has one more signal line USART_CK which can output
synchronous clock than the asynchronous mode.
CLKEN bit of USART_CTRL2 register decides whether to enter the synchronous
mode.
When USART enters the synchronous mode:
HDEN bit of USART_CTRL3 register must be cleared
The start bit and stop bit of the data frame have no clock output
Whether the last data bit of the data frame generates USART_CK
clock is determined by LBCPOEN bit of the register USART_CTRL2
The clock polarity of USART_CK is decided by CPOL bit of
USART_CTRL2 register
The phase of USART_CK is decided by the CPHA bit of
USART_CTRL2
The external CK clock cannot be activated when the bus is idle or the
frame is disconnected
Figure 96 USART Synchronous Transmission Example
Clock input
Data output
Data input
RX
TX
CK
USART
Slave
Figure 97 USART Synchronous Transmission Timing Diagram (DBLCFG=10)
DBLCFG=10(7-bit data）
RX(from slave device)
TX(from master device)
Start
bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Stop
bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
CK(CPOL=0,CPHA=0)
CK(CPOL=0,CPHA=1)
CK(CPOL=1,CPHA=0)
CK(CPOL=1,CPHA=1)
