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Field
Name
R/W
Description
20
USART5 R/W
USART5 Reset
0: No effect
1: Reset
21
I2C1
R/W
I2C1 Reset
0: No effect
1: Reset
22
I2C2
R/W
I2C2 Reset
0: No effect
1: Reset
27:23
Reserved
28
PMU
R/W
Power Interface Reset
0: No effect
1: Reset
31:29
Reserved
AHB peripheral clock enable register (RCM_AHBCLKEN)
Offset address: 0x14
Reset value: 0x0000 0014
Access: Access in the form of word, half word and byte, without wait cycle
All bits can be reset or cleared by software.
Note: When the peripheral clock is not enabled, the software cannot read the
value of the peripheral register, and the value returned is always 0x0.
Field
Name
R/W
Description
0
DMA
R/W
DMA Clock Enable
0: Disable
1: Enable
1
Reserved
2
SRAM
R/W
SRAM Interface Clock Enable
Enable SRAM clock in sleep mode.
0: Disable
1: Enable
3
Reserved
4
FMC
R/W
FMC Clock Enable
Enable the flash interface circuit clock in sleep mode.
0: Disable
1: Enable
5
Reserved
6
CRC
R/W
CRC Clock Enable
0: Disable
1: Enable
16:7
Reserved
