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Geehy SEMICONDUCTOR APM32F030x4x6x8xC, User Manual

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Geehy SEMICONDUCTOR APM32F030x4x6x8xC User Manual Download Page 102

 

www.geehy.com                                                                                                                                              Page  101

 

Figure 25 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode 

CNT_EN

CK_CNT

04

03

02

01

00

01

02

03

04

03

02

01

Counter register 

Counter underrun 

Counter overrun 

CK_PSC

PSC=1

CK_CNT

00

01

0003

0002

0001

0000

0001

0002

0003

Counter overrun 

Update event

PSC=2

Counter register 

Update event

 

Repeat counter REPCNT 

There is no repeat counter REPCNT in the basic/general-purpose timer, which 
means  that  when  the  overrun  event  or  underrun  event  occurs  in  the 
basic/general-purpose timer, an update event will be generated directly; while in 
the  advanced  timer,  because  of  the  existence  of  the  repeat  counter,  when  an 
overrun/unerrrun event occurs to the advanced timer, the update event will be 
generated only when the value of the repeat counter is 0. 

For example, if the advanced timer needs to generate an update event when an 
overrun/underrun event occurs, the value of the repeat counter should be set to 
0. 

If  the  repeat  counter  function  is  used  in  the  count-up  mode,  every  time  the 
counter counts up to AUTORLD, an overrun event will occur. At this time, the 
value of the repeat counter will be decreased by 1, and an update event will be 
generated until the value of the repeat counter is 0. 

That is, when N+1 (N is the value of repeat counter) overrun/underrun events 
occur, an update event will be generated. 

 

Summary of Contents for APM32F030x4x6x8xC

Page 1: ...www geehy com Page 0 User Manual APM32F030x4x6x8xC Arm Cortex M0 based 32 bit MCU Version V1 7...

Page 2: ...Controller SYSCFG 22 4 1 Full Name and Abbreviation Description of Terms 22 4 2 Register Address Mapping 22 4 3 Register Functional Description 22 5 Reset and Clock Management RCM 28 5 1 Full Name an...

Page 3: ...ain Characteristics 77 10 4 Functional Description 78 10 5 Register Address Mapping 78 10 6 Register Functional Description 78 11 General purpose Alternate Function Input Output Pin GPIO AFIO 82 11 1...

Page 4: ...6 1 Introduction 175 16 2 Main Characteristics 175 16 3 Structure Block Diagram 176 16 4 Functional Description 177 16 5 TMR15 Register Address Mapping 188 16 6 TMR15 Register Functional Description 1...

Page 5: ...roduction 246 21 3 Main Characteristics 246 21 4 Functional Description 247 21 5 Register Address Mapping 259 21 6 Register Functional Description 260 22 Internal Integrated Circuit Interface I2C 270...

Page 6: ...ption 317 25 Cyclic Redundancy Check Computing Unit CRC 323 25 1 Introduction 323 25 2 Functional Description 323 25 3 Register Address Mapping 323 25 4 Register Functional Description 324 26 Chip Ele...

Page 7: ...gisters usually include V VALUE D and DATA which are not followed by verbs such as xxPSC and CNT Full Name and Abbreviation Description of Terms Table 1 R W Abbreviation and Description R W Descriptio...

Page 8: ...trl CTRL Controller C Reset RST Stop STOP Set SET Load LD Calibration CAL Initialize INIT Error ERR Status STS Ready RDY Software SW Hardware HW Source SRC System SYS Peripheral PER Address ADDR Direc...

Page 9: ...ry Access DMA Debug MCU DBG MCU General Purpose Input Output Pin GPIO Alternate Function Input Output Pin AFIO Timer TMR Watchdog Timer WDT Independent Watchdog Timer IWDT Windows Watchdog Timer WWDT...

Page 10: ...2 2 System Architecture Block Diagram The main system mainly consists of two master modules and four slave modules The main modules are Arm Cortex M0 core and general purpose DMA The slave modules are...

Page 11: ...le 5 Bus Name Name Instruction System bus Connect the system bus peripheral bus of Arm Cortex M0 core and the bus matrix DMA bus Connect AHB master control interface of DMA and the bus matrix Bus matr...

Page 12: ...OT0 X 0 Main flash memory Flash The main flash memory is mapped to the boot space but it can still be accessed at its original address that is the contents of the flash memory can be accessed in two a...

Page 13: ...e UID and capacity information of main memory area are stored in system memory area with a capacity of 3KB for APM32F030x4x6x8 8KB for APM32F030xC The capacity of the option byte area is 16Bytes 2 Fun...

Page 14: ...0 0FFF 2K Main memory area Main memory area Page 62 0x0801 F000 0x0801 F7FF 2K Fan 31 Main memory area Page 63 0x0801 F800 0x0801 FFFF 2K Main memory area Main memory area Page 126 0x0800 8000 0x0800...

Page 15: ...correct page erase or flash write operation is completed OCF of FMC_STS register will be set If OCIE interrupt is enabled an operation completion interrupt will be triggered Users need to note that t...

Page 16: ...directly written and the corresponding value must be written to FMC_KEY according to the correct sequence to unlock FMC The KEY value is as follows KEY1 0x45670123 KEY2 0xCDEF89AB The wrong writing se...

Page 17: ...its reverse code an option byte error OBE bit of FMC_ register is set to 1 will be triggered and this byte will be set to 0xFF The information of 16 bytes in the option byte area is shown in the tabl...

Page 18: ...4KB 4 pages address of the main memory area 0 Write protection is turned on 1 Write protection is not turned on WRP0 Page 0 31 APM32F030x8 series products Each bit in WRPx controls the write protecti...

Page 19: ...refetch Buffer Enable 0 Disable 1 Enable 5 PBSF R Prefetch Buffer Status Flag 0 In disabled state 1 In enabled state 31 6 Reserved Key register FMC_KEY Offset address 0x04 Reset value xxxx xxxx Field...

Page 20: ...d 31 6 Reserved Control register 2 FMC_CTRL2 Offset address 0x10 Reset value 0x0000 0080 Field Name R W Description 0 PG R W Program Set this bit to 1 to program Flash 1 PAGEERA R W Page Erase Set thi...

Page 21: ...ion 31 0 ADDR W Flash Address In programming operation the bit is written to the address to be programmed in page erasing this bit is written to the page to be erased Option bye control state register...

Page 22: ...eserved 12 nBOOT1 R nBoot1 Mode Configure 13 VDDAMONI R VDDA Monitor 14 SRAMPARITY R SRAM Parity Check 15 Reserved 23 16 DATA0 R Data0 31 24 DATA1 R Data1 Write protection register FMC_WRTPROT Offset...

Page 23: ...egister Address Mapping Register name Description Offset address SYSCFG_CFG1 Configuration register 1 0x00 SYSCFG_EINTCFG1 External interrupt register 1 0x08 SYSCFG_EINTCFG2 External interrupt registe...

Page 24: ...DMA_CH4 12 TMR17DMARMP R W TMR17 DMA Request Remap This bit control remapping request of TMR17 0 No remapping TMR17_CH1 and TMR17_UP DMA_CH1 1 Remapping TMR17_CH1 and TMR17_UP DMA_CH2 15 13 Reserved 1...

Page 25: ...Interrupt Sources Selected for Different Values EINTx 3 0 External interrupt source x000 PA x pin x001 PB x pin x010 PC x pin x011 PD x pin x100 Reserved x101 PF x pin Others Reserved Offset address...

Page 26: ...Table 16 11 8 EINT6 R W EINT6 Configure These bits are controlled by software to be rewritten to select the external interrupt source of EINT6 The selected external interrupt sources represented by v...

Page 27: ...bits are shown in Table 16 7 4 EINT13 R W EINT13 Configure These bits are controlled by software to be rewritten to select the external interrupt source of EINT13 The selected external interrupt sour...

Page 28: ...SRAMEFLG RC_W1 SRAM Parity Error Flag When an SRAM parity error is detected this bit will be set by hardware This bit will be cleared when the software writes 1 0 No SRAM parity check bit error is de...

Page 29: ...ock LSICLK Phase Locked Loop PLL Main clock output MCO Calibrate CAL Trim TRM Clock Security System CSS Non Maskable Interrupt NMI 5 2 Reset Functional Description The supported reset is divided into...

Page 30: ...ntering the stop mode In these two cases if RSTSTDB bit in standby mode or RSTSTOP bit in stop mode in user selection byte is cleared the system will be reset rather than entering the standby or stop...

Page 31: ...t source is as follows Software reset triggered by resetting RTCRST bit in RCM_RTCCTRL Power on reset POR reset A RTC domain reset will occur in case of any of the above events RTC region reset only a...

Page 32: ...e signal can be generated by ordinary function signal transmitter in debugging crystal oscillator and other signal generators the waveform can be square wave sine wave or triangle wave with 40 60 duty...

Page 33: ...startup stage LSECLK clock signal is not released until this bit is set to 1 by hardware If it is allowed in the clock interrupt register an interrupt request can be generated Internal Clock Source Th...

Page 34: ...indicates whether the low speed internal oscillator is stable At startup stage the clock is not released until this bit is set to 1 by hardware If it is allowed in RCM_INT clock interrupt register LSI...

Page 35: ...PCLK is clock signal of the peripheral connected to APB 3 FCLK is running clock of Arm Cortex M0 4 The frequency of AHB APB2 high speed APB and APB1 low speed APB domains can be configured through mu...

Page 36: ...you must wait until the destination clock source is ready i e the destination clock source is stable CSS Clock Security System In order to prevent MCU from normal operation due to external crystal osc...

Page 37: ...isabled Deep sleep mode The system can be debugged by setting the STOP_CLK_STS bit and STANDBY_CLK_STS bit in DBGMCU_CFG The system selects HSICLK as SYSCLK through interrupt in stop mode or reset sta...

Page 38: ...hrough PLL this bit cannot be cleared 0 HSICLK RC oscillator is disabled 1 HSICLK RC oscillator is turned on 1 HSIRDYFLG R High Speed Internal Clock Ready Flag 0 HSICLK RC oscillator is not stable 1 H...

Page 39: ...1 RCM_CFG1 Offset address 0x04 Reset value 0x0000 0000 All bits of this register are set or cleared by software Access Access in the form of word half word and byte with 0 to 2 wait cycles 1 or 2 wai...

Page 40: ...ed as PLL clock source after 2 frequency division 1 HSECLK is used as PLL clock source 17 PLLHSEPSC R W HSECLK Prescaler Factor for PLL Clock Source Refer to Bit 0 of RCM_CFG2 21 18 PLLMULCFG R W PLL...

Page 41: ...ill be cleared 0 No LSECLK ready interrupt 1 LSECLK ready interrupt occurred 2 HSIRDYFLG R HSICLK Ready Interrupt Flag When HSICLK is stable and HSIRDYEN bit is set to 1 this bit will be set to 1 by h...

Page 42: ...LLRDYEN R W PLL Ready Interrupt Enable Enable PLL ready interrupt 0 Disable 1 Enable 13 HSI14RDYEN R W HSICLK14 Ready Interrupt Enable Enable the internal 14MHz RC oscillator ready interrupt 0 Disable...

Page 43: ...et 4 1 Reserved 5 USART6 R W USART6 Reset 0 No effect 1 Reset 8 6 Reserved 9 ADC R W ADC Reset 0 No effect 1 Reset 10 Reserved 11 TMR1 R W TMR1 Timer Reset 0 No effect 1 Reset 12 SPI1 R W SPI1 Reset 0...

Page 44: ...ed 4 TMR6 R W Timer 6 Reset 0 No effect 1 Reset 5 TMR7 R W Timer 7 Reset 0 No effect 1 Reset 7 6 Reserved 8 TMR14 R W Timer 14 Reset 0 No effect 1 Reset 10 9 Reserved 11 WWDT R W Window Watchdog Reset...

Page 45: ...ord half word and byte without wait cycle All bits can be reset or cleared by software Note When the peripheral clock is not enabled the software cannot read the value of the peripheral register and t...

Page 46: ...00 Access Access in the form of word half word and byte Usually there is no wait cycle However when the peripheral on the APB2 bus is accessed the waiting state will be inserted until the APB2 periphe...

Page 47: ...Enable 0 Disable 1 Enable 31 23 Reserved APB peripheral clock enable register 1 RCM_APBCLKEN1 Offset address 0x1C Reset value 0x0000 0000 Access Access in the form of word half word and byte Usually...

Page 48: ...ble 13 12 Reserved 14 SPI2 R W SPI 2 Clock Enable 0 Disable 1 Enable 16 15 Reserved 17 USART2 R W USART 2 Clock Enable 0 Disable 1 Enable 18 USART3 R W USART 3 Clock Enable 0 Disable 1 Enable 19 USART...

Page 49: ...al Clock Bypass Mode Configure Bypass mode refers to the mode in which external clock is used as the LSECLK clock source otherwise the resonator is used as the LSECLK clock source 0 Non bypass mode 1...

Page 50: ...Enable 1 LSIRDYFLG R Low Speed Internal Oscillator Ready Flag When LSICLK is stable this bit is set to 1 by hardware and when it is unstable it is cleared by hardware 0 Not ready 1 Ready 22 2 Reserve...

Page 51: ...tchdog is reset it is set to 1 by hardware and cleared by software by writing RSTFLGCLR bit 0 Not occur 1 Occurred 31 LPWRRSTFLG R Low Power Reset Occur Flag When low power management is reset it is s...

Page 52: ...word half word and byte without wait cycle Field Name R W Description 1 0 USART1SEL R W USRAT1 Clock Source Select Set or cleared by software The default value is 00 00 PCLK is used as USART1CLK 01 S...

Page 53: ...ace can turn on HSICLK14 oscillator which is set or cleared by hardware 0 Can be turned on 1 Cannot be turned on 7 3 HSI14TRM R W HSICLK14 Trim The product has been calibrated to 14MHz 1 when leaving...

Page 54: ...for stable operation of a system with working voltage of 2 0 3 6V and 1 5V power supply can be provided through the built in voltage regulator 6 3 Structure Block Diagram Figure 6 Power Supply Control...

Page 55: ...area stops power supply and except for the standby circuit the content of register and SRAM will be lost 6 4 1 2 VDDA power domain Power the ADC HSICLK LSICLK TempSensor PLL and reset module through...

Page 56: ...data saved are after wake up users can choose the most appropriate low power mode according to their needs The following table shows the difference among three low power modes Table 22 Difference amon...

Page 57: ...program after WFI instruction If the system is woken up by event it will directly execute the program after WFE instruction Stop mode The characteristics of stop mode are shown in the table below Tabl...

Page 58: ...PMU_CTRL Power control register 0x00 PMU_CSTS Power control state register 0x04 6 6 Register Functional Description Power control register PMU_CTRL Offset address 0x00 Reset value 0x0000 0000 cleared...

Page 59: ...UP pin 0 Not occur 1 Occurred Note Enable the WKUP pin and an event will be detected when the WKUP pin is at high level 1 SBFLG R Standby Flag This bit is set to 1 by hardware and can only be cleared...

Page 60: ...errupt channels excluding 16 Cortex M0 interrupt lines 2 4 programmable priority levels use 2 bit interrupt priority level 3 Low delay exception and interrupt processing 4 Power management control 5 R...

Page 61: ...BRK UP TRG and COM interrupt TMR1_CC 14 Can be set 0x0000_0078 TMR1 capture compareinterrupt 15 0x0000_007C Reserved TMR3 16 Can be set 0x0000_0080 TMR3 interrupt TMR6 17 Can be set 0x0000_0084 TMR6...

Page 62: ...hardware interrupt External signal 1 Set the trigger mode allow the interrupt request and enable corresponding peripheral interrupt line enable in NVIC 2 When an edge consistent with the configuration...

Page 63: ...ripheral interrupt and the pending bit of peripheral NVIC interrupt channel clear the pending register in the NVIC interrupt 2 Wake up through EINT line events external hardware event Configure EINT l...

Page 64: ...terrupt event register 0x10 EINT_IPEND Interrupt pending register 0x14 8 4 Register Functional Description Interrupt mask register EINT_IMASK Offset address 0x00 Reset value 0x7F84 0000 Field Name R W...

Page 65: ...and Interrupt of Line x 0 Disable 1 Enable 18 Reserved 22 19 FTENx R W Enable the falling trigger event and interrupt on Line x Falling Trigger Event Enable and Interrupt of Line x 0 Disable 1 Enable...

Page 66: ...enerates an interrupt event Pending register EINT_IPEND Offset address 0x14 Reset value 0xXXXX XXXX Field Name R W Description 17 0 IPENDx RC_W1 Interrupt Pending Occur of Line x Flag Whether the sele...

Page 67: ...channel has three event flags and independent interrupts 6 Support circular transmission mode 7 The number of data transmission is programmable up to 65535 9 3 Functional Description DMA Request If t...

Page 68: ...el only when the corresponding remapping bit of SYSCFG_CFGR1 register is cleared 2 This DMA request is mapped to the DAM channel only when the corresponding remapping bit of SYSCFG_CFGR1 register is s...

Page 69: ...1 applies only to APM32F030x4x6x8 Table 2 applies only to APM32F030xC DMA Channel 9 3 2 1 Transmission data are programmable The data transmitted by DMA are programmable up to 65535 and the transmissi...

Page 70: ...0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Source Target Figure 11 Transmission Width with Source of 32bits and Target of 8bits 0x0 0x1 Data0 Data1 0x2 0x3 Data2 Data3 0x4 0x5 Data4...

Page 71: ...Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Source Target Figure 13 Transmission Width with Source of 16bits and Target of 32bits 0x0 0x1 Data0 Data1 0x2 0x3 Data2...

Page 72: ...nt depends on the selected data width 9 3 2 4 Transmission mode There are two channel configuration modes non circular mode and circular mode Non circular mode When the data transmission is finished t...

Page 73: ...to put the memory to the memory mode The DMA operation in this mode is performed under the condition of no peripheral request The CHEN bit of the configuration register DMA_CHCFGx is set to 1 and afte...

Page 74: ...half transmission interrupt HT is generated on the channel these bits are set to 1 by hardware write 1 and clear on the corresponding bit of DMA_INTFCLR 0 Not generate 1 Generate 19 15 11 7 3 TERRFLGx...

Page 75: ...W DMA Channel Enable 0 Disable 1 Enable 1 TCINTEN R W All Transfer Complete Interrupt Enable 0 Disable 1 Enable 2 HTINTEN R W Half Transfer Complete Interrupt Enable 0 Disable 1 Enable 3 TERRINTEN R W...

Page 76: ...e channel is configured to auto reload mode it will be automatically reloaded to the previously configured value if the register is 0 data transmission will not occur regardless of whether the channel...

Page 77: ...MA channel selection register DMA_CHSEL only apply to APM32F030xC Offset address 0xA8 Reset value 0x0000 0000 Field Name R W Description 3 0 CHSEL1 R W DMA Channel 1 Select DMA request mapping of Chan...

Page 78: ...the query is completed the core and peripheral operation can be restored to continue to execute the program Supported debugging interface serial interface Note The hardware debug interface included i...

Page 79: ...access Reset value 0xXXXX XXXX Field Name R W Description 11 0 EQR R Equipment Recognition This field indicates device ID 15 12 Reserved 31 16 WVR R Wafer Version Recognition This field indicates the...

Page 80: ...ved Debug MCU APB1 freeze register DBGMCU_APB1F This register is used to configure MCU during debugging Involve some APB peripherals Freeze the timer counter Freeze I2C SMBus timeout Freeze supporting...

Page 81: ...ved Debug MCU APB2 freeze register DBGMCU_APB2F This register is used to configure MCU during debugging Involve some APB peripherals Freeze the timer counter This register is reset asynchronously by P...

Page 82: ...age 81 Field Name R W Description 18 TMR17_STS R W Configure TMR17 Work Status When Core is in Halted Whether TMR17 counter continues to work when the core stops work 0 Continue to work 1 Stop working...

Page 83: ...annel Metal Oxide Semiconductor P MOS N channel Metal Oxide Semiconductor N MOS 11 2 Main Characteristics 1 Input mode Floating input Pull up input Pull down input 2 Output mode Push pull output Open...

Page 84: ...on the I O port will be configured as floating input mode After reset the debug pin is in AF pull up or pull down state PA14 SWCLK in pull down mode PA13 SWDIO in pull up mode Input Mode In the input...

Page 85: ...tput drive mode push pull open drain can be selected In output mode Schmitt trigger is opened Activate output buffer By configuring the pull up pull down register GPIOx_PUPD select whether to use pull...

Page 86: ...ivate schmitt trigger input By configuring the pull up pull down register GPIOx_PUPD select whether to use pull up pull down resistors The data on the I O pin is sampled in each AHB clock cycle and st...

Page 87: ...the GPIOx_ODATA register If BS and BC bits of GPIOx_BSC are set to 1 at the same time BS bit has the priority GPIOx_ BSC register can change the corresponding bit of the GPIOx_ODATA register and GPIOx...

Page 88: ...multiplexing function in GPIOx_MODE When the I O port is configured with multiplexing function its input and output mode is as follows Open the output buffer Output buffer is driven by peripheral Acti...

Page 89: ...is powered off it will lose PC13 PC14 PC15 GPIO function and at this time if the configuration of GPIO is not configured by RTC PC13 14 PC15 pin will be set as analog input mode For detailed informat...

Page 90: ...31 0 OSSELy 1 0 R W PortxPin y Output Speed Select y 0 15 x0 Low speed 01 Medium speed 11 High speed The speed of configuration I O port is written by software Pport pull up pull down register GPIOx_...

Page 91: ...Ay bit is cleared If BSy bit and BCy bit are set at the same time BSy has the priority Port lock register GPIOx_LOCK x A B This register protects the configuration of GPIO from being modified by mista...

Page 92: ...escription 31 0 ALFSELy R W PortxPin y Alternate Function Select y 0 7 These bits can be read by software to configure the multiplexing function of the port ALFSELy selection 0000 AF0 0001 AF1 0010 AF...

Page 93: ...ved Port reset register GPIOx_BR x A D F Offset address 0x28 Reset value 0x0000 0000 Field Name R W Description 15 0 BRy W PortxPin y Reset Configure y 0 15 These bits can only perform write operation...

Page 94: ...imer that can count up down The function of general purpose timer is simpler than that of advanced timer The main differences are the total number of channels the number of complementary output channe...

Page 95: ...ions and Terms of Pins Name Description TMRx_ETR External trigger signal of Timer x TMRx_CH1 TMRx_CH2 TMRx_CH3 TMRx_CH4 Channel 1 2 3 4 of Timer x TMRx_CHyN Complementary output channel y of Timer x T...

Page 96: ...Timer input filter polarity ICx IC1 Input capture ICxPS IC1PS Input capture prescaler TRC Trigger capture BRK Breaking signal OCx OC1 Timer output coparison channel OCxREF OC1REF Output compare refere...

Page 97: ...unter Auto reloading function 2 Clock source selection Internal clock External input External trigger Internal trigger 3 Input capture function Counting function PWM input mode measurement of pulse wi...

Page 98: ...register TMRx_CH4 TMRx_CH3 TMRx_CH2 TMRx_CH1 TMRx_CHx TMRx_CHxN TMRx_CH3 TMRx_CH3N TMRx_CH4 TRGO Other timer DAC ADC ETRF Repeat counter TMRx_ETR 13 4 Functional Description Clock Source Selection The...

Page 99: ...NT 8 bits Counter CNT There are three counting modes for the counter in the advanced timer Count up mode Count down mode Center aligned mode Count up mode Set to the count up mode by CNTDIR bit of con...

Page 100: ...count down mode the counter will start to count down from the value of the auto reload TMRx_AUTORLD every time a pulse is generated the counter will decrease by 1 and when it becomes 0 the counter wil...

Page 101: ...egister Center aligned mode Set to the center aligned mode by CNTDIR bit of configuration control register TMRx_CTRL1 When the counter is in center aligned mode the counter counts up from 0 to the val...

Page 102: ...le in the advanced timer because of the existence of the repeat counter when an overrun unerrrun event occurs to the advanced timer the update event will be generated only when the value of the repeat...

Page 103: ...of the timer first pass through the edge detector and input filter and then into the capture channel Each capture channel has a corresponding capture register When the capture occurs the value of the...

Page 104: ...figured by OCxMOD bit in TMRx_CCMx register and can control the waveform of output signal in output compare mode Output compare application In the output compare mode the position polarity frequency a...

Page 105: ...g Diagram AUTORLD CCx 0CxREF Figure 28 PWM1 Count down Mode Timing Diagram CCx AUTORLD 0CxREF Figure 29 PWM1 Center aligned Mode Timing Diagram AUTORLD CCx 0CxREF In PWM mode 2 if the value of the cou...

Page 106: ...Diagram CCx AUTORLD 0CxREF Figure 32 PWM2 Center aligned Mode Timing Diagram CCx AUTORLD 0CxREF PWM Input Mode PWM input mode is a particular case of input capture In PWM input mode as only TI1FP1 an...

Page 107: ...latched in TMRx_CC1 IC1 capture Cycle The value is latched in TMRx_CC2 0003 0005 Single pulse Mode The single pulse mode is a special case of timer compare output and is also a special case of PWM out...

Page 108: ...hen idle MOEN 0 the output level after the dead time is 0 OCxOIS 1 amd OCxNOIS 1 When idle MOEN 0 the output level after the dead time is 1 4 RMOS bit in TMRx_BDT register Application environment of R...

Page 109: ...put the idle level OSI Output disable output disabled first output the invalid level during the dead zone affected by the polarity and after it is received by dead zone output the idle level OIS Norma...

Page 110: ...ed and the corresponding level is directly output according to the configuration instruction CCxSEL 00 for TMRx_CCMx register set CCx channel as output OCxMOD 100 101 for TMRx_CCMx register set to for...

Page 111: ...Count in both TI1 and TI2 Level of relative signal High Low High Low High Low TI1FP1 Rising edge Count down Count up Count down Count up Falling edge Count up Count down Count up Count down TI2FP2 Ri...

Page 112: ...update the register In the gated mode the enable of the counter depends on the high level of the selected input When the trigger input is high the clock of the counter will be started Once the trigger...

Page 113: ...terrupt when an event occurs during operation Update event counter overrun underrun counter initialization Trigger event counter start stop internal external trigger Capture Compare event Breaking sig...

Page 114: ...able all registers of the advanced timer are mapped to a 16 bit addressable address space Table 44 TMR1 Register Address Mapping Register name Description Offset address TMRx_CTRL1 Control register 1...

Page 115: ...tware to start regular work when it is configured as the trigger mode it can be written to 1 by hardware 1 UD R W Update Disable Update event can cause AUTORLD PSC and CCx to generate the value of upd...

Page 116: ...dify the values loaded to the counter when the buffer is enabled the program modification TMRx_AUTORLD will modify the values loaded to the counter in the next update event 0 Disable 1 Enable 9 8 CLKD...

Page 117: ...OC1 Output Idle State Configure Only the level state after the dead time of OC1 is affected when MOEN 0 and OC1N is realized 0 OC1 0 1 OC1 1 Note When LOCKCFG bit in TMRx_BDT register is at the Level...

Page 118: ...gnal of TRGI as the clock source to drive the counter to work 3 OCCSEL R W OCREF Clear Source Select This bit is used to select OCREF clear source 0 OCREF_CLR 1 ETRF 6 4 TRGSEL R W Trigger Input Signa...

Page 119: ...be used at the same time with external clock mode 2 but TRGI cannot be connected to ETRF in such case when external clock mode 1 and external clock mode 2 are enabled at the same time the input of ex...

Page 120: ...ble 1 Enable 11 CC3DEN R W Capture Compare Channel3 DMA Request Enable 0 Disable 1 Enable 12 CC4DEN R W Capture Compare Channel4 DMA Request Enable 0 Disable 1 Enable 13 COMDEN R W COM DMA Request Ena...

Page 121: ...LG 5 COMIFLG RC_W0 COM Event Interrupt Generate Flag 0 COM event does not occur 1 COM interrupt waits for response After COM event is generated this bit is set to 1 by hardware and cleared by software...

Page 122: ...uest will be generated at this time if CC1IFLG 1 it is required to configure CC1RCFLG 1 2 CC2EG W Capture Compare Channel2 Event Generation Refer to CC1EG description 3 CC3EG W Capture Compare Channel...

Page 123: ...de SPMEN 1 otherwise the following output compare result is uncertain 6 4 OC1MOD R W Output Compare Channel1 Mode Configure 000 Freeze The output compare has no effect on OC1REF 001 The output value i...

Page 124: ...IC1 is mapped on TI2 11 CC1 channel is input and IC1 is mapped on TRC and only works in internal trigger input Note This bit can be written only when the channel is disabled TMRx_CCEN bit CC1EN 0 3 2...

Page 125: ...Note This bit can be written only when the channel is disabled TMRx_CCEN register CC3EN 0 2 OC3FEN R W Output Compare Channel3 Fast Enable 0 Disable 1 Enable This bit is used to improve the response...

Page 126: ...ped on TRC and only works in internal trigger input Note This bit can be written only when the channel is disabled TMRx_CCEN register CC4EN 0 11 10 IC4PSC R W Input Capture Channel 4 Perscaler Configu...

Page 127: ...hen CC1 channel is configured as input This bit together with CC1POL is used to define the polarity of TI1FP1 and TI2FP1 Note 1 On the complementary output channel if this bit is preloaded and CCPEN 1...

Page 128: ...000 Field Name R W Description 7 0 REPCNT R W Repetition Counter Value When the count value of the repeat counter is reduced to 0 an update event will be generated and the counter will start counting...

Page 129: ...cription 15 0 CC4 R W Capture Compare Channel 4 Value Refer to TMRx_CC1 Break and dead time register TMRx_BDT Offset address 0x44 Reset value 0x0000 Note According to the lock setting AOEN BRKPOL BRKE...

Page 130: ...evel is output after the dead time 11 RMOS R W Run Mode Off state Configure Run mode means MOEN 1 disable means CcxEN 0 this bit describes the impact of different values for this bit on the output wav...

Page 131: ...le the address DBADDR 7 of TMRx_CTRL1 means the address of the data to be written read Data transmission will occur to TMRx_CTRL1 address seven registers starting from DBADDR The data transmission wil...

Page 132: ...eristics 1 Timebase unit Counter 16 bit counter count up count down and center aligned count Prescaler 16 bit programmable prescaler Auto reloading function 2 Clock source selection Internal clock Ext...

Page 133: ...H1 TMRx_CHx TRGO Other timer DAC ADC ETRF Repeat counter Output control TMRx_CHx 0Cx 14 4 Functional Description Clock Source Selection The general purpose timer has four clock sources Internal clock...

Page 134: ...r AUTORLD 16 bits Prescaler register PSC 16 bits Counter CNT There are three counting modes for the counter in the general purpose timer Count up mode Count down mode Center aligned mode Count up mode...

Page 135: ...he counter is in count down mode the counter will start to count down from the value of the auto reload TMRx_AUTORLD every time a pulse is generated the counter will decrease by 1 and when it becomes...

Page 136: ...egister Center aligned mode Set to the center aligned mode by CNTDIR bit of configuration control register TMRx_CTRL1 When the counter is in center aligned mode the counter counts up from 0 to the val...

Page 137: ...will drive the counter CNT to count The prescaler has a buffer which can be changed during running Input Capture Input capture channel The general purpose timer has four independent capture compare ch...

Page 138: ...d through capture Output Compare There are eight modes of output compare freeze channel x is valid level when matching channel x is invalid level when matching flip force is invalid force is valid PWM...

Page 139: ...iagram in PWM mode 1 when CCx 5 AUTORLD 7 Figure 47 PWM1 Count up Mode Timing Diagram AUTORLD CCx 0CxREF Figure 48 PWM1 Count down Mode Timing Diagram CCx AUTORLD 0CxREF Figure 49 PWM1 Center aligned...

Page 140: ...the output level will be invalid otherwise it will be valid Set the timing diagram in PWM mode 2 when CCx 5 AUTORLD 7 Figure 50 PWM2 Count up Mode Timing Diagram CCx AUTORLD 0CxREF Figure 51 PWM2 Coun...

Page 141: ...0000 0001 0002 0003 0004 0005 0000 TI1 TMRx_CNT TMRx_CC1 TMRx_CC2 IC1 capture IC2 capture Counter reset IC2 capture Pulse width The value is latched in TMRx_CC1 IC1 capture Cycle The value is latched...

Page 142: ...interface is as follows By setting SMFSEL bit of TMRx_SMCTRL register set the counter to count on the edge of TI1 channel TI2 channel or count on the edge of TI1 and TI2 at the same time Select the po...

Page 143: ...n Count up The external incremental encoder can be directly connected with MCU not needing external interface logic so the comparator is used to convert the differential output of the encoder to digit...

Page 144: ...update the register In the gated mode the enable of the counter depends on the high level of the selected input When the trigger input is high the clock of the counter will be started Once the trigger...

Page 145: ...nerate an interrupt when an event occurs during operation Update event counter overrun underrun counter initialization Trigger event counter start stop internal external trigger Capture Compare event...

Page 146: ...following table all registers of TMR3 are mapped to a 16 bit addressable address space Table 47 TMR3 Register Mapping Register name Description Offset address TMRx_CTRL1 Control register 1 0x00 TMRx_C...

Page 147: ...re 1 UD R W Update Disable Update event can cause AUTORLD PSC and CCx to generate the value of update setting 0 Update event is allowed UEV An update event can occur in any of the following situations...

Page 148: ...le 1 Enable 9 8 CLKDIV R W Clock Divide Factor For the configuration of dead time and digital filter CK_INT provides the clock and the dead time and the clock of the digital filter can be adjusted by...

Page 149: ...nal of TRGI and generates the signal to update the register 101 Gated mode the slave mode timer starts the counter to work after receiving the TRGI high level signal it stops the counter when receivin...

Page 150: ...led 01 ETR signal 2 divided frequency 10 ETR signal 4 divided frequency 11 ETR signal 8 divided frequency 14 ECEN R W External Clock Enable Mode2 0 Disable 1 Enable Setting ECEN bit has the same funct...

Page 151: ...9 CC1DEN R W Capture Compare Channel1 DMA Request Enable 0 Disable 1 Enable 10 CC2DEN R W Capture Compare Channel2 DMA Request Enable 0 Disable 1 Enable 11 CC3DEN R W Capture Compare Channel3 DMA Req...

Page 152: ...re or cleared when reading TMRx_CC1 register 2 CC2IFLG RC_W0 Capture Compare Channel2 i Interrupt Flag Refer to STS_CC1IFLG 3 CC3IFLG RC_W0 Capture Compare Channel3 Interrupt Flag Refer to STS_CC1IFLG...

Page 153: ...e generated at this time if CC1IFLG 1 it is required to configure CC1RCFLG 1 2 CC2EG W Capture Compare Channel2 Event Generation Refer to CC1EG description 3 CC3EG W Capture Compare Channel3 Event Gen...

Page 154: ...r matches the value of the capture compareregister OC1REF will be forced to be at low level 011 Output flaps when matching When the value of the counter matches the value of the capture compareregiste...

Page 155: ...001 DIV 1 N 2 0010 DIV 1 N 4 0011 DIV 1 N 8 0100 DIV 2 N 6 0101 DIV 2 N 8 0110 DIV 4 N 6 0111 DIV 4 N 8 1000 DIV 8 N 6 1001 DIV 8 N 8 1010 DIV 16 N 5 1011 DIV 16 N 6 1100 DIV 16 N 8 1101 DIV 32 N 5 11...

Page 156: ...ct This bit defines the input output direction and the selected input pin 00 CC4 channel is output 01 CC4 channel is input and IC4 is mapped on TI4 10 CC4 channel is input and IC4 is mapped on TI3 11...

Page 157: ...is enabled 1 CC1POL R W Capture Compare Channel1 Output Polarity Configure When CC1 channel is configured as output 0 OC1 high level is valid 1 OC1 low level is valid When CC1 channel is configured a...

Page 158: ...le Refer to CCEN_CC1EN 13 CC4POL R W Capture Compare Channel4 Output Polarity Configure Refer to CCEN_CC1POL 14 Reserved 15 CC4NPOL R W Capture Compare Channel4 Output Polarity Configure Refer to CCEN...

Page 159: ...load is disabled OC1PEN 0 for TMRx_CCM1 register the written value will immediately affect the output compare results If the output compare preload is enabled OC1PEN 1 for TMRx_CCM1 register the writt...

Page 160: ...DR 7 of TMRx_CTRL1 means the address of the data to be written read Data transmission will occur to TMRx_CTRL1 address seven registers starting from DBADDR The data transmission will change according...

Page 161: ...up count down and center aligned count Prescaler 16 bit programmable prescaler Auto reloading function 2 Clock source Internal clock 3 Timer function Input capture Output compare PWM output mode Force...

Page 162: ...to the count up mode by CNTDIR bit of configuration control register TMRx_CTRL1 When the counter is in count up mode the counter will count up from 0 every time a pulse is generated the counter will i...

Page 163: ...rt to count down from the value of the auto reload TMRx_AUTORLD every time a pulse is generated the counter will decrease by 1 and when it becomes 0 the counter will start to count again from TMRx_AUT...

Page 164: ...egister Center aligned mode Set to the center aligned mode by CNTDIR bit of configuration control register TMRx_CTRL1 When the counter is in center aligned mode the counter counts up from 0 to the val...

Page 165: ...ster and after frequency division the clock will drive the counter CNT to count The prescaler has a buffer which can be changed during running Input Capture Input capture channel The general purpose t...

Page 166: ...d through capture Output Compare There are eight modes of output compare freeze channel x is valid level when matching channel x is invalid level when matching flip force is invalid force is valid PWM...

Page 167: ...iagram in PWM mode 1 when CCx 5 AUTORLD 7 Figure 64 PWM1 Count up Mode Timing Diagram AUTORLD CCx 0CxREF Figure 65 PWM1 Count down Mode Timing Diagram CCx AUTORLD 0CxREF Figure 66 PWM1 Center aligned...

Page 168: ...the output level will be invalid otherwise it will be valid Set the timing diagram in PWM mode 2 when CCx 5 AUTORLD 7 Figure 67 PWM2 Count up Mode Timing Diagram CCx AUTORLD 0CxREF Figure 68 PWM2 Coun...

Page 169: ...ter 0x14 TMRx_CCM1 Capture Compare mode register 1 0x18 TMRx_CCEN Capture Compare enable register 0x20 TMRx_CNT Counter register 0x24 TMRx_PSC Prescaler register 0x28 TMRx_AUTORLD Auto reload register...

Page 170: ...it 00 tDTS tCK_INT 01 tDTS 2 tCK_INT 10 tDTS 4 tCK_INT 11 Reserved 15 10 Reserved DMA Interrupt enable register TMRx_DIEN Offset address 0x0C Reset value 0x0000 Field Name R W Description 0 UIEN R W U...

Page 171: ...d In the count down mode the counter reads the value of TMRx_AUTORLD in center aligned mode or count up mode the counter will be cleared 1 CC1EG W Capture Compare Channel1 Event Generation 0 Invalid 1...

Page 172: ...be at high level 010 The output value is low when matching When the value of the counter matches the value of the capture compareregister OC1REF will be forced to be at low level 011 Output flaps when...

Page 173: ...apture Compare Channel1 Output Polarity Configure When CC1 channel is configured as output 0 OC1 high level is valid 1 OC1 low level is valid When CC1 channel is configured as input CC1POL and CC1NPOL...

Page 174: ...CNT fCK_PSC PSC 1 Auto reload register TMRx_AUTORLD Offset address 0x2C Reset value 0xFFFF Field Name R W Description 15 0 AUTORLD R W Auto Reload Value When the value of auto reload is empty the coun...

Page 175: ...Reset value 0x0000 Field Name R W Description 1 0 RMPSEL R W Timer Input 1 Remap Select 00 TMR14 channel 1 is connected to GPIO Refer to the data manual 01 TMR14 channel 1 is connected to RTCCLK 10 T...

Page 176: ...up Prescaler 16 bit programmable prescaler Repeat counter 16 bit repeat counter Auto reloading function 2 Clock source selection Internal clock External input only applicable to TMR15 Internal trigge...

Page 177: ...PSC Prescaler CNT counter Auto reload register Externa l clock mode 1 Interna l clock mode TRC ITR0 ITR1 ITR2 ITR3 ITR TRGI TI1FP1 TI2FP2 TI1F_ED Internal clock CK_INT CK_PSC CK_CNT TRGO Other timer...

Page 178: ...ltering and the synchronization or cascading between timers can be realized The master mode timer can reset start stop or provide clock for the slave mode timer Timebase Unit The time base unit in the...

Page 179: ...ose timer because of the existence of the repeat counter when an overrun unerrrun event occurs to the general purpose timer the update event will be generated only when the value of the repeat counter...

Page 180: ...aler which is used to set how many events to capture at a time Input capture application Input capture is used to capture external events and can give the time flag to indicate the occurrence time of...

Page 181: ...w level or flip by configuring the OCxMOD bit in TMRx_CCMx register and the CCxPOL bit in the output polarity TMRx_CCEN register When CCxIFLG 1 in TMRx_STS register if CCxIEN 1 in TMRx_DIEN register a...

Page 182: ...iagram in PWM mode 1 when CCx 5 AUTORLD 7 Figure 74 PWM1 Count up Mode Timing Diagram AUTORLD CCx 0CxREF Figure 75 PWM1 Count down Mode Timing Diagram CCx AUTORLD 0CxREF Figure 76 PWM1 Center aligned...

Page 183: ...the output level will be invalid otherwise it will be valid Set the timing diagram in PWM mode 2 when CCx 5 AUTORLD 7 Figure 77 PWM2 Count up Mode Timing Diagram CCx AUTORLD 0CxREF Figure 78 PWM2 Coun...

Page 184: ...ut Mode 0005 0000 0001 0002 0003 0004 0005 0000 TI1 TMRx_CNT TMRx_CC1 TMRx_CC2 IC1 capture IC2 capture Counter reset IC2 capture Cycle width The value is latched in TMRx_CC1 IC1 capture Cycle The valu...

Page 185: ...hen idle MOEN 0 the output level after the dead time is 0 OCxOIS 1 amd OCxNOIS 1 When idle MOEN 0 the output level after the dead time is 1 4 RMOS bit in TMRx_BDT register Application environment of R...

Page 186: ...put the idle level OSI Output disable output disabled first output the invalid level during the dead zone affected by the polarity and after it is received by dead zone output the idle level OIS Norma...

Page 187: ...ode In the forced output mode the compare result is ignored and the corresponding level is directly output according to the configuration instruction CCxSEL 00 for TMRx_CCMx register set CCx channel a...

Page 188: ...p and provide clock source for the counter of the slave mode timer Figure 85 Interconnection of TMR15 and Other Timers TRGO TMR16 Master mode controller TRGO TMR3 Master mode controller TRGO TMR17 Mas...

Page 189: ...5_REPCNT Repeat count register 0x30 TMR15_CC1 Channel 1 capture compare register 0x34 TMR15_CC2 Channel 2 capture compare register 0x38 TMR15_BDT Break and dead time register 0x44 TMR15_DCTRL DMA cont...

Page 190: ...program modification TMR15_AUTORLD will modify the values loaded to the counter in the next update event 0 Disable 1 Enable 9 8 CLKDIV R W Clock Divide Factor For the configuration of dead time and d...

Page 191: ...er is at the Level 1 2 or 3 this bit cannot be modified 9 OC1NOIS R W OC1N Output Idle State Configure Only the level state after the dead time of OC1 is affected when MOEN 0 and OC1N is realized 0 OC...

Page 192: ...input edge detector TIF_ED 101 Channel 1 post filtering timer input TI1FP1 110 Channel 2 post filtering timer input TI2FP2 111 External trigger input ETRF 7 MSMEN R W Master slave Mode Enable 0 Inval...

Page 193: ...er configure UEG 1 on TMR15_CEG register to generate update event and the counter needs to be initialized by software 3 URSSEL 0 and UD 0 on TMRx_CTRL1 register generate update event when the counter...

Page 194: ...by hardware Note When an update event is generated the counter of the prescaler will be cleared but the prescaler factor remains unchanged In the count down mode the counter reads the value of TMRx_AU...

Page 195: ...nternal trigger input Note This bit can be written only when the channel is disabled TMR15_CCEN register CC1EN 0 2 OC1FEN R W Output Compare Channel1 Fast Enable 0 Disable 1 Enable This bit is used to...

Page 196: ...apped on TI1 11 CC2 channel is input and IC2 is mapped on TRC and only works in internal trigger input Note This bit can be written only when the channel is disabled TMR15_CCEN register CC2EN 0 10 OC2...

Page 197: ...CC1EN R W Capture Compare Channel1 Output Enable When the capture compare channel 1 is configured as output 0 Output is disabled 1 Output is enabled When the capture compare channel 1 is configured as...

Page 198: ...ble Refer to CCEN_CC1EN 5 CC2POL R W Capture Compare Channel2 Output Polarity Configure Refer to CCEN_CC1POL 6 Reserved 7 CC2NPOL R W Capture Compare Channel2 Complementary Output Polarity Configure R...

Page 199: ...nabled OC1PEN 1 for TMRx_CCM1 register the written value will affect the output compare result when an update event is generated Channel 2 capture compare register TMR15_CC2 Offset address 0x38 Reset...

Page 200: ...e dead time 11 RMOS R W Run Mode Off state Configure Run mode means MOEN 1 disable means CcxEN 0 this bit describes the impact of different values for this bit on the output waveform when MOEN 1 and C...

Page 201: ...itted while the address DBADDR 7 of TMRx_CTRL1 means the address of the data to be written read Data transmission will occur to TMRx_CTRL1 address seven registers starting from DBADDR The data transmi...

Page 202: ...at count register 0x30 TMRx_CC1 Channel 1 capture compare register 0x34 TMRx_BDT Break and dead time register 0x44 TMRx_DCTRL DMA control register 0x48 TMRx_DMADDR DMA address register of continuous m...

Page 203: ...nabled the program modification TMRx_AUTORLD will modify the values loaded to the counter in the next update event 0 Disable 1 Enable 9 8 CLKDIV R W Clock Divide Factor For the configuration of dead t...

Page 204: ...Idle State Configure Only the level state after the dead time of OC1 is affected when MOEN 0 and OC1N is realized 0 OC1N 0 1 OC1N 1 Note When LOCKCFG bit in TMRx_BDT register is at the Level 1 2 or 3...

Page 205: ...pture compare channel 1 is configured as output 0 No matching occurred 1 The value of TMRx_CNT matches the value of TMRx_CC1 When the capture compare channel 1 is configured as input 0 Input capture d...

Page 206: ...nter is stored in TMRx_CC1 register configure CC1IFLG 1 and if CC1IEN and CC1DEN bits are also set the corresponding interrupt and DMA request will be generated at this time if CC1IFLG 1 it is require...

Page 207: ...The output value is high when matching When the value of counter CNT matches the value CCx of capture compare register OC1REF will be forced to be at high level 010 The output value is low when matchi...

Page 208: ...hannel 1 is configured as input This bit determines whether the value CNT of the counter can be captured and enter TMRx_CC1 register 0 Capture is disabled 1 Capture is enabled 1 CC1POL R W Capture Com...

Page 209: ...x0000 Field Name R W Description 15 0 PSC R W Prescaler Value Clock frequency of counter CK_CNT fCK_PSC PSC 1 Auto reload register TMRx_AUTORLD Offset address 0x2C Reset value 0xFFFF Field Name R W De...

Page 210: ...16 TDTS For example assuming TDTS 125ns 8MHZ the dead time setting is as follows If the step time is 125ns the dead time can be set from 0 to 15875ns If the step time is 250ns the dead time can be se...

Page 211: ...xN or force the output of idle state 1 When CCxEN and CCxNEN bits of the TMRx_CCEN register are set turn on OCx and OCxN output When the break input is valid it is cleared by hardware asynchronously N...

Page 212: ...the second register is the LSB bit of the first data and the data will still be transmitted to seven registers 15 13 Reserved DMA address register of continuous mode TMRx_DMADDR Offset address 0x4C R...

Page 213: ...ram Figure 86 Basic Timer Structure Block Diagram Counter CNT Auto reload register PSC Prescaler Trigger processing Controller TRGO CK_PSC CK_CNT Internal clockCK_INT 17 4 Functional Description Clock...

Page 214: ...URSSEL bit in TMRx_CTRL1 register When an update event occurs both the auto reload register and the prescaler register will be updated Figure 87 Counter Timing Diagram the internal clock division fac...

Page 215: ...by software to start regular work when it is configured as the trigger mode it can be written to 1 by hardware 1 UD R W Update Disable Update event can cause AUTORLD PSC and CCx to generate the value...

Page 216: ...Offset address 0x10 Reset value 0x0000 Field Name R W Description 0 UIFLG RC_W0 Update Event Interrupt Generate Flag 0 Update event interrupt does not occur 1 Update event interrupt occurs When the c...

Page 217: ...leared 15 1 Reserved Note The state of external I O pin connected to the standard OCx channel depends on the state of the OCx channel and the GPIO and AFIO registers Counter register TMRx_CNT Offset a...

Page 218: ...data receiving IRTMR Transmit IRTMR is internally connected to TMR16 and TMR17 and the specific block diagram is as follows Figure 88 IRTMR Structure Block Diagram TMR16_CH1 IRTMR Information to be s...

Page 219: ...dog consists of an 8 bit prescaler IWDT_PSC 12 bit count down counter 12 bit reload register IWDT_CNTRLD key register IWDT_KEY state register IWDT_STS and window register IWDT_WIN The independent watc...

Page 220: ...gister IWDT_KEY Configure IWDT_PSC prescaler register write the value within 0 7 to IWDT_PSC The value of wait state register IWDT_STS is updated to 0x00 Configuration window register IWDT_WIN the val...

Page 221: ...own counter CNT Configuration register CFG 4096 CNT CFG Write WWDT CTRL Reset CNTT6 bit clear PCLK1 PCLK1 from RCM clock controller 1 2 4 8 TBPSC Functional Description Enable window watchdog timer th...

Page 222: ...alculation formula of window watchdog timer timeout is as follows TWWDT TPCLK1 2WTB T 5 0 1 Wherein TWWDT WWDT timeout TPCLK1 Clock cycle of APB in ms Table 56 Minimum Maximum timeout when PCLK1 36MHz...

Page 223: ...to prevent the watchdog from resetting Write 0xCCCC and the watchdog will be enabled the hardware watchdog is unrestricted by this command word The read out value is 0x0000 31 16 Reserved Prescaler r...

Page 224: ...ue of VDD power supply domain will be returned so if you want to read data you should ensure STS_WINUFLG 0 31 12 Reserved Note When the reload setting prescaler setting and window value resetting are...

Page 225: ...x3F WWDT reset will be generated 7 WWDTEN R S Window Watchdog Enable This bit is set to 1 by software and can be cleared by hardware only after reset When WWDTEN 1 WWDT can generate a reset 0 Disable...

Page 226: ...ame R W Description 0 EWIFLG RC_W0 Early Wakeup Interrupt Occur Flag 0 Not occur 1 When the counter value reaches 0x40 it is set to 1 by hardware if the interrupt is not enabled the bit will also be s...

Page 227: ...second time and date registers with BCD coding as well as corresponding alarm registers and can realize timestamp function together with external pins It supports clock calibration function and time...

Page 228: ...estamp controller LSECLK HSECLK 32 LSICLK Asynchronous prescaler 7 bit RTC calibration Synchronous prescaler 15bit Wake up prescaler 2 4 8 16 16bit reload wake up counter RTC output Subsecond Calendar...

Page 229: ...d by RTC Pin configuration and function RTC_ALARM Output enable RTC_CALIB Output enable RTC_TAMP1 Input enable RTC_TS Input enable PC13EN PC13VAL RTC_ALARM Open drain output 1 No effect No effect No e...

Page 230: ...it Clock source RTC has three clock sources RTC_CLK External LSECLK crystal oscillator External HSECLK crystal oscillator Internal LSICLK Different clock sources are configured through RCM peripheral...

Page 231: ..._CLK as a calibration cycle by default In addition 219 and 218 RTC_CLK can be set as a calibration cycle through the registers CALW16 and CALW8 When LSECLK is used as RTC_CLK clock source the calibrat...

Page 232: ...fRTC_CLK or the system is woken from low power mode it is recommended to read the calendar directly from the calendar counter If RSFLG bit is not set to 1 when reading the calender just at the stage...

Page 233: ...as multiple tamper detection pins and each pin is enabled by a register bit separately In order to detect real tamper events better signal filtering can be configured and tamper detection polarity can...

Page 234: ...generally used to observe the accuracy of RTC clock source and the observed value is used to calibrate the clock source 512Hz and 1Hz signal output sources can be selected through CALOSEL bit of RTC_C...

Page 235: ...Unit in BCD Format Setup 6 4 SECT R W Second Ten s Place Unit in BCD Format Setup 7 Reserved 11 8 MINU R W Minute Ones Unit in BCD Format Setup 14 12 MINT R W Minute Ten s Place Unit in BCD Format Set...

Page 236: ...eld Name R W Description 2 0 WUCLKSEL R W Wakeup Clock Select 000 RTC 16 001 RTC 8 010 RTC 4 011 RTC 2 10x clk_spre usually 1Hz 11x clk_spre usually 1Hz and add 216 to WUAUTORE counter value 3 TSETECF...

Page 237: ...nt time increases by 1 hour to calibrate the winter time variation 18 BAKP R W Backup Value Setup This bit indicates whether the summer time has changed and is written by the user 19 CALOSEL R W Calib...

Page 238: ...are when shifting operation is pending SOPFLG 1 or is in the mode that the shadow register is ignored RCMCFG 1 this bit is cleared by hardware in initialized mode or this bit can be cleared by softwar...

Page 239: ...0x10 Power on reset value 0x007F 00FF System reset 0xXXXX XXXX Field Name R W Description 14 0 SPSC R W Synchronous Prescaler Coefficient ck_spre frequency ck_apre frequency SPSC 1 15 Reserved 22 16 A...

Page 240: ...Alarm A 19 16 HRU R W Hour Ones Unit in BCD Format Setup 21 20 HRT R W Hour Ten s Place Unit in BCD Format Setup 22 TIMEFCFG R W Time Format Configure 0 AM or 24 hour system 1 PM 23 HRMEN R W Alarm A...

Page 241: ...Delay seconds SFSEC SPSC 1 When it takes effect at the same time with ADD1SECEN the advance clock will be added by a fraction of a second the specific added value is determined by the following formul...

Page 242: ...on reset value 0x0000 0000 System reset 0xXXXX XXXX Field Name R W Description 3 0 DAYU R Day Ones Unit in BCD Format Setup 5 4 DAYT R Day Ten s Place Unit in BCD Format Setup 7 6 Reserved 11 8 MONU...

Page 243: ...t cannot be set to 1 at the same time with CAL16CFG bit When CAL8CFG 1 RECALF 1 0 is always 00 15 ICALFEN R W Increase Calibration Frequency Enable 0 RTCCLK pulse is not increased 1 One RTCCLK pulse i...

Page 244: ...Frequency Select These bits determine the sampling frequency of each input of RTC_TAMPx 0x0 RTCCLK 32768 0x1 RTCCLK 16384 0x2 RTCCLK 8192 0x3 RTCCLK 4096 0x4 RTCCLK 2048 0x5 RTCCLK 1024 0x6 RTCCLK 51...

Page 245: ...23 PC15EN R W PC15 Mode Enable 0 PC15 is controlled by GPIO configuration register and in standby mode PC15 is floating 1 When LSECLK is disabled PC15 is forced to push pull output mode 31 24 Reserve...

Page 246: ...13 is not involved and only SUBSEC 12 0 is involved 0xE When comparing with alarm A SUBSEC 14 is not involved and only SUBSEC 13 0 is involved 0xF When comparing the alarm A 15 SUBSEC bits all take pa...

Page 247: ...rts multiprocessor communication USART not only supports standard asynchronous transmission and receiving mode but also supports synchronous one way communication and hardware flow control mode USART...

Page 248: ...iple interrupt sources The transmit register is empty Transmission is completed CTS changed The receive register cannot be empty Overload error Bus idle Parity error Noise error Overrun error Frame er...

Page 249: ...bit USART data frame 0 0 Start bit 8 bit data stop bit 0 1 Start bit 7 bit data odd even parity check bit stop bit 1 0 Start bit 9 bit data stop bit 1 1 Start bit 8 bit data odd even parity check bit...

Page 250: ...aud rate of communication in USART_BR register 5 Set UEN bit of USART_CTRL1 register to enable USART Wait for TXBEFLG bit of USART_STS register to be set to 1 6 Enable TXEN bit in USART_CTRL1 register...

Page 251: ...k frame starts the break frame will not be transmitted To transmit two consecutive break frames the TXBFQ bit should be set after the stop bit of the previous break symbol 21 4 3 4 Idle frame The idle...

Page 252: ...tem before USART is enabled 1 The clock source is selected according to the transmission speed and the possibility of use of USART in low power mode 2 The clock source frequency is fCK The range of co...

Page 253: ...ng process of the receiver Set NEFLG flag on the rising edge of RXBNEFLG bit of USART_STS register Invalid data is transmitted from the shift register to USART_RXDATA register In single byte communica...

Page 254: ...e rising edge 2 For all characters starting with 10xx in this case measure the length of the start bit and the first data bit the duration of the falling edge to ensure better accuracy when the signal...

Page 255: ...2 Data 3 Data 4 Idle frame Address flag detection WUPMCFG 1 If the address flag bit is 1 this byte is regarded as the address The storage address of lower four bits of the address bytes will first be...

Page 256: ...es USART_CK clock is determined by LBCPOEN bit of the register USART_CTRL2 The clock polarity of USART_CK is decided by CPOL bit of USART_CTRL2 register The phase of USART_CK is decided by the CPHA bi...

Page 257: ...CFG0 1 DBLOGO 1 9 bit data RX from slave device TX from master device Start bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 CK CPOL 0 CPHA...

Page 258: ...ignal to turn on the control terminal of the external transceiver Lead time The time interval between the driver enable signal and the start bit of the first byte Controlled by DLTEN 4 0 of USART_CTRL...

Page 259: ...ble DMA channel Interrupt Request Table 67 USART Interrupt Request Interrupt event Event flag bit Enable bit The receive register cannot be empty RXBNEFLG RXBNEIEN Overload error OVREFLG Line idle is...

Page 260: ...SART6 Hardware flow control Multi buffer communication DMA Multi processor communication Synchronous Half duplex single line mode Receiving timeout interrupt Support the automatic baud rate detection...

Page 261: ...rent operation and the prescaler and output of USART will stop working immediately The setting for USART will not be reset but the state flag in USART_STS will be reset 1 Reserved 2 RXEN R W Receive E...

Page 262: ...CFG0 R W Data Bits Length Configure 0 1 start bit 8 data bits n stop bits 1 1 start bit 9 data bits n stop bits Set 1 or clear 0 by software This bit cannot be modified during transmission of data 13...

Page 263: ...ield Name R W Description 3 0 Reserved 4 ADDRLEN R W Slave Address Length Configure 0 4 bit address 1 7 bit address This bit field can be set only when USART is not enabled 7 5 Reserved 8 LBCPOEN R W...

Page 264: ...verter on TX line Set or cleared by software This bit can be set only when USART is not enabled 18 BINVEN R W Binary Data Inversion Enable 0 Positive Direct logic 0 L 1 H 1 Negative Reverse logic 0 H...

Page 265: ...off or USAR is not enabled Control register 3 USART_CTRL3 Offset address 0x08 Reset value 0x0000 Field Name R W Description 0 ERRIEN R W Error interrupt Enable 0 Disable 1 Enabled when any bit among F...

Page 266: ...om overrunning and being covered RXBNEFLG will not be set In smart card mode as a result no DMA request will be issued so wrong data will not be transmitted but the next correct data will be transmitt...

Page 267: ...W Auto Baud Rate Detection Request Set this bit the ABRDFLG flag will be cleared and an automatic baud rate detection will be conducted when the data is received next time 1 TXBFQ W Transmit Break Fr...

Page 268: ...can be cleared by reading the TXDATA register or setting RXDFQ 6 TXCFLG R Transmit Data Complete Flag 0 Transmit data is not completed 1 Transmit data is completed After the last frame of data is tran...

Page 269: ...mit Break Frame Flag 0 Not transmit 1 Will transmit If TXBFQ bit is set this bit can be set to 1 by software when transmitting the stop bit of the break frame this bit is cleared by hardware 19 RXWFMU...

Page 270: ...Reserved Receive data register USART_RXDATA Offset address 0x24 Reset value 0xXXXX Field Name R W Description 8 0 RXDATA R Receive Data Value Setup Include the received data byte Provide the parallel...

Page 271: ...unication protocol In physical implementation I2C bus is composed of two signal lines SDA and SCL and a ground wire These two signal lines can be used for bidirectional transmission Two signal lines S...

Page 272: ...imeout management 12 Can select an independent clock source 22 4 Structure Block Diagram Figure 101 I2C1 Functional Structure Diagram I2CCLK SYSCLK HSICLK Data controller Clock controller Shift regist...

Page 273: ...r GPIO Logic GPIO Logic I2C2_SDA I2C2_SCL APB bus 22 5 Functional Description I2C Physical Layer Figure 103 Commonly Used I2C Communication Connection Diagram I2C master I2C slave 1 I2C slave 2 I2C sl...

Page 274: ...mode is adopted to determine which device occupies the bus 7 Can program setup and hold time and program the high level time and low level time of SCL in I2C I2C Protocol Layer Characteristics of pro...

Page 275: ...transmit data to the slave the data length is one byte and every time the master transmits one byte of data it needs to wait for the answer signal transmitted by the slave After all the bytes have bee...

Page 276: ...filter Input delay of digital filter Delay caused by synchronous I2C_CLK clock of SCL tSYNC2 depends on SCL rising slope Input delay of analog filter Input delay of digital filter Delay caused by sync...

Page 277: ...s 16x250 ns 4 0 s 4x125 ns 500 ns 2x125 ns 250 ns tSCL 100 s 10 s 2500ns 875ns DATAHT 0x2 0x2 0x3 0 tDATAHT 2x250 ns 500 ns 2x250 ns 500 ns 3x125 ns 375 ns 0ns DATAT 0x4 0x4 0x3 0x1 tDATAT 5x250 ns 12...

Page 278: ...ituations The received address matches the enabled slave address and SCL clock is pulled down and will be released when ADDRMFLG flag is cleared by software ADDRMFLG flag bit can be cleared by setting...

Page 279: ...col and one system has only one HOST Bus protocol There are 11 possible command protocols for any given device and one device can communicate with any or all of 11 protocols Address resolution protoco...

Page 280: ...e or a master device occupies the clock the total low clock time is greater than t LOW SEXT Therefore the test condition of this parameter is that the slave is the only communication target of a full...

Page 281: ...be generated Overrun Underrun error flag bit OVRURFLG When clock extension is disabled CLKSTRETCHD 1 underrun or overrun error will be detected under the following conditions in slave mode When recei...

Page 282: ...are set by software when the slave address has been transmitted DMA cannot be used for transmission When all data are transmitted by DMA DMA must be initialized before START bit is set to 1 Slave mode...

Page 283: ...lear register 0x1C I2C_PEC PEC register 0x20 I2C_RXDATA Receive data register 0x24 I2C_TXDATA Transmit data register 0x28 22 7 Register Functional Description Control register 1 I2C_CTRL1 Offset addre...

Page 284: ...le 1 Enable 15 DMARXEN R W DMA Receive Enable 0 Disable 1 Enable 16 SBCEN R W Slave Byte Control Enable 0 Disable 1 Enable 17 CLKSTRETCHD R W Slave Mode Clock Stretching Disable 0 Enable 1 Disable Thi...

Page 285: ...smission 1 Read transmission 11 SADDRLEN R W Slave Address Length Configure 0 7 bit addressing mode 1 10 bit addressing mode 12 ADDR10 R W Master Transmit 10 Bit Address Header Configure 0 Transmit 10...

Page 286: ...ly when START bit is not set 24 RELOADEN R W NUMBYT Reload Mode Enable It can be set to 1 and cleared by software 0 Transmission is over after transmission of NUMBYT bytes 1 Reload NUMBYT after transm...

Page 287: ...ss register 2 I2C_ADDR2 Offset address 0x0C Reset value 0x0000 0000 Field Name R W Description 0 Reserved 7 1 ADDR2 7 1 R W Master Address Setup Master address bit 7 1 10 8 ADDR2MSK R W Masks Master A...

Page 288: ...high and low level counter tTIMINGPSC TIMINGPSC 1 x tI2C_CLK Note This register can be set only when I2CEN bit is not set Timeout register I2C_TIMEOUT Offset address 0x14 Reset value 0x0000 0000 Fiel...

Page 289: ...s to generate TXINTFLG flag bit it can be cleared by hardware when I2CEN 0 2 RXBNEFLG R Receive Data Buffer Not Empty Flag 0 The receive buffer is empty 1 The receive buffer is not empty This bit can...

Page 290: ...n occurs This bit can be set to 1 by hardware if overrun underrun error occurs in slave mode when CLKSTRETCHD 1 be cleared by software by setting OVRURCLR bit and be cleared by hardware when I2CEN 0 1...

Page 291: ...l be cleared 4 NACKCLR W Receive Not Acknowledge Flag Clear Set this bit and NACKFLG flag bit of I2C_STS register will be cleared 5 STOPCLR W Stop Bit Detection Flag Clear Set this bit and STOPFLG fla...

Page 292: ...hardware when I2CEN 0 31 8 Reserved Receive data register I2C_RXDATA Offset address 0x24 Reset value 0x0000 0000 Field Name R W Description 7 0 RXDATA R 8 Bit Receive Data Byte Data byte received from...

Page 293: ...llows chips to communicate with external devices in half duplex full duplex synchronous and serial modes and can work in master or slave mode 23 3 Main Characteristics 1 Master and slave operation wit...

Page 294: ...Slave hardware NSS mode The NSS signal is set to low level as the chip selection signal of the slave Communication format In SPI communication receiving data and transmitting data can be carried out a...

Page 295: ...right aligned In the process of communication only the bits within the data word length range will be output with the clock NSS mode Software NSS mode Select to enable or disable this mode by configur...

Page 296: ...slave mode In slave mode SCK pin receives the serial clock transmitted from the master device Configuration of slave mode Configure MSMCFG 0 in SPI_CTRL1 register and set it as slave mode Select the...

Page 297: ...eneral purpose I O MISO in master mode MOSI in slave mode Receive only mode Turn off SPI output function by setting RXOMEN bit in SPI_CTRL1 register Release the send pin MOSI in master mode MISO in sl...

Page 298: ...sed MISO transmits Bidirectional receiving mode of slave device BMEN 1 BMOEN 0 MOSI receives MISO is not used Figure 107 Connection in Full Duplex Mode Master device SCK MOSI NSS MISO Slave device SCK...

Page 299: ...RXFIFO will be regarded to be empty and in the similar way the write access to the data frame to be transmitted is managed by TXBEFLG event When TXFIFO is less than or equal to half its capacity RXBN...

Page 300: ...e set by configuring NSSPEN bit of SPI_CTRL1 register this mode take effect only when SPI is configured as Motorola master mode and captures the first edge In transmitting of this mode NSS pulse is ge...

Page 301: ...g SPI_DATA register Sequence of clearing CRC values 1 Disable SPI SPIEN 0 2 Clear CRCEN bit 3 Set CRCEN bit to 1 4 Enable SPI SPIEN 1 Note When SPI works in slave mode the software must enable CRC ope...

Page 302: ...an error occurred during transmission SPI disable After data transmission is over end the communication by closing SPI module When data are being transmitted or there are data in TXFIFO it is not all...

Page 303: ...r an interrupt will be generated Busy flag BSYFLG BSYFLG flag is set and cleared by hardware which can indicate the state of SPI communication layer When BSYFLG 1 it indicates SPI is communicating BSY...

Page 304: ...error flag bit CRCEFLG Enable CRC operation by setting CRCEN bit of SPI_CTRL1 register and CRC error flag can check whether the received data are valid When the value transmitted by SPI_TXCRC register...

Page 305: ...a register 0x0C SPI_CRCPOLY SPI CRC polynomial register 0x10 SPI_RXCRC SPI receive CRC register 0x14 SPI_TXCRC SPI transmit CRC register 0x18 23 6 Register Functional Description These peripheral regi...

Page 306: ...high 9 SSEN R W Software Slave Device Enable 0 Software NSS mode is disabled and the internal NSS level is determined by external NSS pin 1 Software NSS mode is enabled and the internal NSS level is...

Page 307: ...r DMA Enable When RXDEN 1 once RXBNEFLG flag is set DMA request will be issued 0 Disable 1 Enable 1 TXDEN R W Transmit Buffer DMA Enable When this bit is set once TXBEFLG flag is set DMA request will...

Page 308: ...010 11 bits 1011 12 bits 1100 13 bits 1101 14 bits 1110 15 bits 1111 16 bits Note When reserved bit is written by software the value will be forced to be 0111 8 bits 12 FRTCFG R W FIFO Reception Thres...

Page 309: ...ed This bit is set by hardware and it can be cleared by writing 0 to this bit by software 6 OVRFLG R Overrun Occur Flag 0 Not occur 1 Occurred This bit is set by hardware and it can be cleared by writ...

Page 310: ...nomial of CRC computing which can be modified and the reset value is 0x0007 SPI receive CRC register SPI_RXCRC Offset address 0x14 Reset value 0x0000 Field Name R W Description 15 0 RXCRC R Receive Da...

Page 311: ...www geehy com Page 310 Field Name R W Description Note When BSYFLG bit is set to 1 the value of reading RXCRC register may be wrong...

Page 312: ...el category External GPIO input channel One internal temperature sensor VSENSE input channel One internal reference voltage VREFINT input channel 5 High performance 12 bit 10 bit 8 bit or 6 bit config...

Page 313: ...After calibration is completed CAL bit is automatically cleared by hardware The calibration factor is read in CDATA 6 0 bit of register ADC_DATA ADC Conversion Mode 24 3 3 1 Single conversion mode In...

Page 314: ...annel 0 is converted and generates an EOCFLG event 2nd trigger Channel 1 is converted and generates an EOCFLG event 3rd trigger Channel 5 is converted and generates an EOCFLG event DISCEN bit is set t...

Page 315: ...dge Data Register The data can be left aligned or right aligned which is determined by DALIGCFG bit of configuration register ADC_CFG1 ADC conversion results can be left aligned or right aligned and s...

Page 316: ...ta conversion management The software controls data conversion Every time the conversion is completed EOCFLG will be set to 1 and the conversion results will be read from ADC_DATA register Then OVRMAG...

Page 317: ...thod of adaptive ADC speed and adaptive system reading ADC data speed 24 3 11 2 Automatic shutdown mode This mode can greatly reduce the application power consumption and is suitable for applications...

Page 318: ...Sequence Flag This bit is set to 1 by hardware and cleared by software 0 Sequence conversion not completed 1 Sequence conversion completed 4 OVREFLG RC_W1 ADC Overrun Event Flag This bit is set to 1...

Page 319: ...enabled Note ADCEN bit can be set by software only when all bits of ADC_CTRL register are 0 1 ADCD R S ADC Disable This bit is set to 1 by software and cleared by hardware 0 Invalid 1 Disable ADC and...

Page 320: ...a Resolution Configure 00 12 bits 01 10 bits 10 8 bits 11 6 bits 5 DALIGCFG R W Data Alignment Configure 0 Right alignment 1 Left alignment 8 6 EXTTRGSEL R W External Trigger Event Select These bits a...

Page 321: ...og Watchdog Channel Select These bits are used to configure the input channel for the analog watchdog to monitor ADC 00000 Channel 0 00001 Channel 1 10010 Channel 18 Other values Reserved not used Not...

Page 322: ...WDHT 11 0 R W Analog Watchdog High Threshold 31 28 Reserved Note These bits can be rewritten only when STARTCEN 0 ADC channel selection register ADC_CHSEL Offset address 0x28 Reset value 0x0000 0000 F...

Page 323: ...CFG Offset address 0x308 Reset value 0x0000 0000 Field Name R W Description 21 0 Reserved 22 VREFEN R W VREFINT Enable 0 Disable 1 Enable 23 TSEN R W Temperature Sensor Enable 0 Disable 1 Enable 31 24...

Page 324: ...th can be dynamically adjusted to reduce the number of times of calculating and writing The high and low levels of input data can be reversed in order to adapt to different little endian and big endia...

Page 325: ...e 0x0000 0000 Field Name R W Description 0 RST R S Reset CRC Calculation Unit Set the data register to 0xFFFF FFFF It can only set this bit which shall be automatically cleared by hardware 4 1 Reserve...

Page 326: ...www geehy com Page 325 Field Name R W Description 31 0 VALUE R W Initial CRC Value The CRC initial value is programmable and this bit is used to set the CRC initial value...

Page 327: ...e the unique ID under no circumstances According to different usage users can choose to read the identity in byte half word or word 26 2 Register Functional Description 96 bit Unique Chip ID Base addr...

Page 328: ...d read write function of GPIO port reset register 3 Modify the bit 31 13 of TMR14_option register to 31 2 4 Modify 10011 to 10010 in 30 26 of ADC configuration register 1 5 Modify the reset value of C...

Page 329: ...words or graphics with or TM in this document are trademarks of Geehy Other product or service names displayed on Geehy products are the property of their respective owners 2 No Intellectual Property...

Page 330: ...LAWS OF THE COUNTIRIES OF THE PRODUCTS SUPPLIERS GEEHY GEEHY DISTRIBUTORS AND USERS USERS ON BEHALF OR ITSELF SUBSIDIARIES AND AFFILIATED ENTERPRISES SHALLAGREE AND PROMISE TO ABIDE BY ALLAPPLICABLE...

Page 331: ...www geehy com Page 330 versions of the document 2020 2022 Geehy Semiconductor Co Ltd All Rights Reserved...

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