![Geehy SEMICONDUCTOR APM32F030x4x6x8xC User Manual Download Page 148](http://html1.mh-extra.com/html/geehy-semiconductor/apm32f030x4x6x8xc/apm32f030x4x6x8xc_user-manual_573629148.webp)
www.geehy.com Page 147
Field
Name
R/W
Description
0: Count up
1: Count down
6:5
CAMSEL R/W
Center Aligned Mode Select)
In the center-aligned mode, the counter counts up and down alternately;
otherwise, it will only count up or down. Different center-aligned modes affect
the timing of setting the output compare interrupt flag bit of the output
channel to 1; when the counter is disabled (CNTEN=0), select the
center-aligned mode.
00: Edge alignment mode
01: Center-aligned mode 1 (the output compare interrupt flag bit of output
channel is set to 1 when counting down)
10: Center-aligned mode 2 (the output compare interrupt flag bit of output
channel is set to 1 when counting up)
11: Center-aligned mode 3 (the output compare interrupt flag bit of output
channel is set to 1 when counting up/down)
7
ARPEN
R/W
Auto-reload Preload Enable
When the buffer is disabled, the program modification TMRx_AUTORLD will
immediately modify the values loaded to the counter; when the buffer is
enabled, the program modification TMRx_AUTORLD will modify the values
loaded to the counter in the next update event.
0: Disable
1: Enable
9:8
CLKDIV
R/W
Clock Divide Factor
For the configuration of dead time and digital filter, CK_INT provides the
clock, and the dead time and the clock of the digital filter can be adjusted by
setting this bit.
00
:
t
DTS
=t
CK_INT
01
:
t
DTS
=2×t
CK_INT
10
:
t
DTS=
4×t
CK_INT
11: Reserved
15:10
Reserved
Control register 2 (TMRx_CTRL2)
Offset address: 0x04
Reset value: 0x0000
Field
Name
R/W
Description
2:0
Reserved
3
CCDSEL
R/W
Capture/compare DMA Select
0: Send DMA request of CCx when CCx event occurs
1: Send DMA request of CCx when an update event occurs
6:4
MMSEL
R/W
Master Mode Signal Select
The signals of timers working in master mode can be used for TRGO,
which affects the work of timers in slave mode and cascaded with master
timer, and specifically affects the configuration of timers in slave mode.
000: Reset; the reset signal of master mode timer is used for TRGO
001: Enable; the counter enable signal of master mode timer is used for
TRGO
010: Update; the update event of master mode timer is used for TRGO
011: Compare pulses; when the master mode timer captures/compares
successfully (CCxIFLG=1), a pulse signal is output for TRGO
100: Comparison mode 1; OC1REF is used to trigger TRGO
101: Comparison mode 2; OC2REF is used to trigger TRGO
110: Comparison mode 3; OC3REF is used to trigger TRGO