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Load option byte reset
Power reset
A system reset will occur in case of any of the above events. Besides, the reset
event source can be identified by viewing the reset flag bit in RCM_CSTS
(control/state register).
Generally speaking, when the system is reset, the values of all registers except
the reset flag bit of RCM_CSTS will be reset to the reset value.
Software reset
Software can be reset by putting SYSRESETREQ in Arm
®
Cortex
®
-
M0+ interrupt
application and reset control register to "1".
Low-power management reset
Low-power management may reset in two cases, one is when entering the
standby mode, and the other is when entering the stop mode. In these two cases,
if RSTSTDB bit (in standby mode) or RSTSTOP bit (in stop mode) in user
selection byte is cleared, the system will be reset rather than entering the
standby or stop mode.
For more information about user option bytes, refer to the chapter of "Flash
memory".
Load option byte reset
The load byte reset is triggered by OBLOAD bit in FMC_CTRL2 register which is
controlled by software.
5.2.1.2
"System Reset" reset circuit
The reset source is used in the NRST pin, which remains low in reset
process.
The internal reset source generates a delay of at least 20μs pulse on the
NRST pin through the pulse generator, which causes the NRST to maintain
the level to generate reset; the external reset source directly pulls down the
NRST pin level to generate reset.
The "system reset" reset circuit is shown in the figure below.
