www.geehy.com Page 144
Figure 57 Interconnection of TMR3 and Other Timers
TRGO
TMR15
Master mode
controller
TRGO
TMR1
Master mode
controller
TRGO
TMR14
Master mode
controller
TMR3
Slave mode controller
TS=000
TS=010
TS=011
ITR0
ITR2
ITR3
Master
timer
Slave timer
When the timers are interconnected:
A timer can be used as the prescaler of other register
Another register can be started by the enable signal of a timer
Another register can be started by the update event of a timer
Another register can be selected by the enable of a timer
Two timers can be synchronized by an external trigger
Interrupt and DMA Request
The timer can generate an interrupt when an event occurs during operation
Update event (counter overrun/underrun, counter initialization)
Trigger event (counter start, stop, internal/external trigger)
Capture/Compare event
Some internal interrupt events can generate DMA requests, and special
interfaces can enable or disable DMA requests.
Clear OCxREF signal when external events occur
This function is used for output compare and PWM mode.
In one channel, the high level of ETRF input port will reduce the signal of
OCxREF to low level, and the OCxCEN bit in capture/compare register
TMRx_CCMx is set to 1, and OCxREF signal will remain low until the next
update event.
Set TMR3 to PWM mode, close the external trigger prescaler, and disable the
external trigger mode 2; when ETRF input is high, set OCxCEN=0, and the
output OCxREF signal is shown in the figure below.
