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Figure 82 Register Structural Relationship Affecting Output Waveform
MOEN=1
run mode run mode
MOEN=0
idle mode idle
mode
RMOS=1
RMOS=0
CCxEN/CCxNEN=1
CCxEN/CCxNEN=0
Off state/Invalid state (OFF state),
output level is controlled by polarity;
output invalid level
Output disable, output disabled,
output 0
CCxEN/CCxNEN=1
CCxEN/CCxNEN=0
IMOS=1
IMOS=0
CCxEN/CCxNEN=1
CCxEN/CCxNEN=0
CCxEN/CCxNEN=1
CCxEN/CCxNEN=0
Output disable, output disabled, first
output 0 during the dead zone, and after it
is received by dead zone, output the idle
level OSI
Output disable, output disabled, first
output the invalid level during the dead
zone (affected by the polarity), and after
it is received by dead zone, output the
idle level OIS
Normal output
Normal output
Breaking Function
The signal source of breaking is clock fault event and external input interface.
Besides, the BRKEN bit in TMRx_BDT register can enable the breaking function,
and the BRKPOL bit can configure the polarity of breaking input signal.
When a breaking event occurs, the output pulse signal level can be modified
according to the state of the relevant control bit.
Figure 83 Breaking Event Timing Diagram
CCxPOL=0,OCxOIS=0
OCx
OCxREF
OCx
OCx
OCx
CCxPOL=0,OCxOIS=1
CCxPOL=1,OCxOIS=0
CCXPOL=1,OCxOIS=1
Break
