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Figure 7 Power-on Reset and Power-down Reset Oscillogram
POR
PDR
Reset
POR
PDR
Hysteresis
time
Hysteresis
voltage
V
DD
/V
DDA
t
Power Consumption Control
6.4.3.1
Reduce the power consumption in low-power mode
There are three low-power modes: sleep mode, stop mode and standby mode.
The power consumption is reduced by closing the core and clock source and
setting the voltage regulator.
The power consumption, wake-up start time, wake-up mode and data storage of
each low-power mode are different; the lower the power consumption is, the
longer the wake-up time is, the less the wake-up mode is, the less the data
saved are after wake-up; users can choose the most appropriate low-power
mode according to their needs. The following table shows the difference among
three low-power modes.
Table 22 Difference among "Sleep Mode, Stop Mode and Standby Mode"
Mode
Instruction
Entry mode
Wake-up mode
Voltage
regulator
Effect on
1.5V area
clock
Effect on
V
DD
area
clock
Sleep
Arm
®
Cortex
®
-
M0+
core stops, and
all peripherals
including the
core peripheral
are still working
Call WFI
instruction
Any interrupt
Open
Ony the
core clock is
turned off
and it has
no effect on
other clocks
and ADC
clocks
None
Call WFE
instruction
Wake-up event
Open
None
Stop
All clocks have
stopped
PDDSCFG and
LPDSCFG bits
+SLEEPDEEP
bit +WFI or WFE
Anny external
interrupt
Turn on or
be in
low-power
mode
Close
clocks of all
1.5V areas
The
oscillator
of HSICLK
and
