www.geehy.com Page 215
Field
Name
R/W
Description
0: Disable
1: Enable
6:4
Reserved
7
ARPEN
R/W
Auto-reload Preload Enable
When the buffer is disabled, the program modification TMRx_AUTORLD will
immediately modify the values loaded to the counter; when the buffer is
enabled, the program modification TMRx_AUTORLD will modify the values
loaded to the counter in the next update event.
0: Disable
1: Enable
15:8
Reserved
DMA/Interrupt enable register (TMRx_DIEN)
Offset address: 0x0C
Reset value: 0x0000
Field
Name
R/W
Description
0
UIEN
R/W
Update interrupt Enable
0: Disable
1: Enable
7:1
Reserved
8
UDIEN
R/W
Update DMA Request Enable
0: Disable
1: Enable
15:9
Reserved
State register (TMRx_STS)
Offset address: 0x10
Reset value: 0x0000
Field
Name
R/W
Description
0
UIFLG RC_W0
Update Event Interrupt Generate Flag
0: Update event interrupt does not occur
1: Update event interrupt occurs
When the counter value is reloaded or reinitialized, an update event will be
generated. The bit is set to 1 by hardware and cleared by software; update
events are generated in the following situations:
(1) UD=0 on TMRx_CTRL1 register, and when the value of the repeat
counter overruns/underruns, an update event will be generated;
(2) URSSEL=0 and UD=0 on TMRx_CTRL1 register, configure UEG=1 on
TMRx_CEG register to generate update event, and the counter needs to be
initialized by software;
(3) URSSEL=0 and UD=0 on TMRx_CTRL1 register, generate update event
when the counter is initialized by trigger event.
15:1
Reserved
Control event generation register (TMRx_CEG)
Offset address: 0x14
Reset value: 0x0000
