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Field
Name
R/W
Description
18
HSEBCFG
R/W
High Speed External Clock Bypass Configure
Bypass mode refers to the mode in which external clock is used as the
HSECLK clock source; otherwise the resonator is used as the HSECLK
clock source.
0: Non-bypass mode
1: Bypass mode
19
CSSEN
R/W
Clock Security System Enable
0: Disable
1: Enable
23:20
Reserved
24
PLLEN
R/W
PLL Enable
When entering the standby and stop mode, this bit is cleared by the
hardware; when PLLCLK has been configured (or in the process of
configuration) as the clock source of the system clock, this bit cannot be
cleared; in other cases, it cane set 1 or clear 0 by the software.
0: PLL is disabled
1: PLL is enabled
25
PLLRDYFLG
R
PLL Clock Ready Flag
PLL is set to 1 by hardware after it is locked.
0: PLL is unlocked
1: PLL is locked
31:26
Reserved
Clock configuration register 1 (RCM_CFG1)
Offset address: 0x04
Reset value: 0x0000 0000
All bits of this register are set or cleared by software.
Access: Access in the form of word, half word and byte, with 0 to 2 wait cycles.
1 or 2 wait cycles are inserted only when the access occurs during clock
switching.
Field
Name
R/W
Description
1:0
SCLKSEL
R/W
System Clock Source Select
When returning from stop or standby mode or the HSECLK directly or
indirectly used as system clock fails, the hardware selects HSICLK as
system clock by force (if the clock security system has been started)
00: HSICLK is used as system clock
01: HSECLK is used as system clock
10: PLLCLK is used as system clock
11: Reserved
3:2
SCLKSELSTS
R
System Clock Selection Status
Indicate which clock source is used as system clock; set 1 or clear 0 by
the hardware.
00: HSICLK is used as system clock
01: HSECLK is used as system clock
10: PLLCLK output is used as system clock
11: Unavailable
7:4
AHBPSC
R/W
AHB Clock Prescaler Factor Configure
Control the prescaler factor of AHB clock.
0xxx: No frequency division for SYSCLK
