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Field
Name
R/W
Description
Note: Once LOCK level (LOCKCFG bit in TMRx_BDT register) is set to 1, 2
or 3, these bits cannot be modified.
9:8
LOCKCFG R/W
Lock Write Protection Mode Configure
00: Without Lock write protection level; the register can be written directly
01: Lock write protection level 1
It cannot be written to DTS, BRKEN, BRKPOL and AOEN bits of
TMRx_BDT, and OCxOIS and OCxNOIS bits of TMRx_CTRL2 register.
10: Lock write protection level 2
It is not allowed to write to all bits with protection level 1 and write to the
CCxPOL and OCxNPOL bits in TMRx_CCEN register and the RMOS
and IMOS bits in TMRx_BDT register.
11: Lock write protection level 3
It is not allowed to write to all bits with protection level 2, and write to the
OCxMOD and OCxPEN bits of TMRx_CCMx register.
Note: After system reset, the lock write protect bit can only be written once.
10
IMOS
R/W
Idle Mode Off-state Configure
Idle mode means MOEN=0; disable means CcxEN=0; this bit describes
the impact of different values for this bit on the output waveform when
MOEN=0 and CcxEN changes from 0 to 1.
0: OCx/OCxN output is disabled
1: If CCxEN=1, the invalid level is output during the dead time (the specific
level value is affected by the polarity configuration), and the idle level is
output after the dead time
11
RMOS
R/W
Run Mode Off-state Configure
Run mode means MOEN=1; disable means CcxEN=0; this bit describes
the impact of different values for this bit on the output waveform when
MOEN=1 and CcxEN changes from 0 to 1.
0: OCx/OCxN output is disabled
1: OCx/OCxN first outptus invalid level (the specific level value is affected
by the polarity configuration)
12
BRKEN
R/W
Break Function Enable
0: Disable
1: Enable
Note: When the protection level is 1, this bit cannot be modified.
13
BRKPOL
R/W
Break Polarity Configure
0: The break input BRK is valid at low level
1: The break input BRK is valid at high level
Note: When the protection level is 1, this bit cannot be modified. Writing to
this bit requires an APB clock delay before it can be used.
14
AOEN
R/W
Automatic Output Enable
0: MOEN can only be set to 1 by software
1: MOEN can be set to 1 by software or be automatically set to 1 in next
update event (breaking input is ineffective)
Note: When the protection level is 1, this bit cannot be modified.
15
MOEN
R/W
PWM Main Output Enable
0: Disable the output of OCx and OCxN or force the output of idle state
1: When CCxEN and CCxNEN bits of the TMRx_CCEN register are set,
turn on OCx and OCxN output
When the break input is valid, it is cleared by hardware asynchronously.
Note: Setting to 1 by software or setting to 1 automatically depends on
AOEN bit of the TMRx_BDT register.
DMA control register (TMRx_DCTRL)
Offset address: 0x48
Reset value: 0x0000
