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In the PWM input mode, the PWM signal enters from TMRx_CH1, and the signal
will be divided into two channels, one can measure the cycle and the other can
measure the duty cycle. In the configuration, it is only required to set the polarity
of one channel, and the other will be automatically configured with the opposite
polarity.
In this mode, the slave mode controller should be configured as the reset mode
(SMFSEL bit of TMRx_SMCTRL register).
Figure 33 Timing Diagram in PWM Input Mode
0005
0000
0001
0002
0003
0004
0005
0000
TI1
TMRx_CNT
TMRx_CC1
TMRx_CC2
IC1 capture
IC2 capture
Counter reset
IC2 capture
Pulse width
The value is latched
in TMRx_CC1
IC1 capture
Cycle
The value is latched
in TMRx_CC2
0003
0005
Single-pulse Mode
The single-pulse mode is a special case of timer compare output, and is also a
special case of PWM output mode.
Set SPMEN bit of TMRx_CTRL1 register, and select the single-pulse mode.
After the counter is started, a certain number of pulses will be output before the
update event occurs. When an update event occurs, the counter will stop
counting, and the subsequent PWM waveform output will no longer be changed.
After a certain controllable delay, a pulse with controllable pulse width is
generated in single-pulse mode through the program. The delay time is defined
by the value of TMRx_CCx register; in the count-up mode, the delay time is CCx
and the pulse width is AUTORLD-CCx; in the count-down mode, the delay time
is AUTORLD-CCx and the pulse width is CCx.
