Geehy SEMICONDUCTOR APM32F030x4x6x8xC, User Manual

Page: 38 / 331

www.geehy.com Page 37
Register name Description Offset address
RCM_RTCCTRL RTC domain control register 0x20
RCM_CSTS Control/State register 0x24
RCM_IORST I/O pin reset register 0x28
RCM_CFG2 Clock configuration register 2 0x2C
RCM_CFG3 Clock configuration register 3 0x30
RCM_CTRL2 Clock control register 2 0x34
5.5
Register Functional Description
Clock control register 1 (RCM_CTRL1)
Offset address: 0x00
Reset value: 0x0000 XX83; X means undefined
Access: Access in the form of word, half word and byte, without wait cycle
Field Name R/W Description
0 HSIEN R/W
High Speed Internal Clock Enable
Set 1 or clear 0 by software.
HSICLK is an RC oscillator. When one of the following conditions occurs,
it will be set to 1 by the hardware: power-on start, software reset,
wake-up from standby mode, wake-up from stop mode, failure of
external high-speed clock source (as system clock or providing system
clock through PLL). When HSICLK is used as system clock or provides
system clock through PLL, this bit cannot be cleared.
0: HSICLK RC oscillator is disabled
1: HSICLK RC oscillator is turned on
1 HSIRDYFLG R
High Speed Internal Clock Ready Flag
0: HSICLK RC oscillator is not stable
1: HSICLK RC oscillator is stable
2 Reserved
7:3 HSITRM R/W
High Speed Internal Clock Trim
The product has been calibrated to 8MHz±1% when leaving the factory.
However, it changes as the temperature and voltage changes, but the
frequency of HSICLK RC oscillator can be adjusted by HSITRM[4:0].
15:8 HSICAL R
High Speed Internal Clock Calibrate
It will be calibrated to 8MHz±1% before leaving the factory. When the
system is started up, the calibration parameters will be automatically
written to the register.
16 HSEEN R/W
High Speed External Clock Enable
When entering the standby or stop mode, this bit is cleared by hardware
and HSECLK is turned off; when HSECLK is used as system clock
source or the system clock is provided through PLL, this bit cannot be
cleared.
0: HSECLK is disabled
1: HSECLK is enabled
17 HSERDYFLG R
High Speed External Clock Ready Flag
When HSECLK is stable, this bit is set to 1 by hardware and cleared by
software.
0: HSECLK is not stable
1: HSECLK is stable