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7
Nested Vector Interrupt Controller (NVIC)
7.1
Full Name and Abbreviation Description of Terms
Table 27 Full Name and Abbreviation Description of Terms
Full name in English
English abbreviation
Non Maskable Interrupt
NMI
7.2
Introduction
The Cortex-M0+ core in the product integrates nested vectored interrupt
controller (NVIC), which is closely coupled with the core, and can handle
exceptions and interrupts and power management control efficiently and with low
delay. Please see
Cortex-M0+ Technical Reference Manual
for more instructions
about NVIC.
7.3
Main Characteristics
（
1
）
32 maskable interrupt channels (excluding 16 Cortex-M0+ interrupt lines)
（
2
）
4 programmable priority levels (use 2-bit interrupt priority level)
（
3
）
Low-delay exception and interrupt processing
（
4
）
Power management control
（
5
）
Realization of system control register
7.4
Interrupt and Exception Vector Table
Table 28 Interrupt and Exception Vector Table
Name
Vector No.
Priority
Vector address
Description
-
-
-
0x0000_0000
Reserved
RST
-
-
3
0x0000_0004
Reset
NMI
-
-
2
0x0000_0008
Non-maskable interrupt
Hardware fault
-
-
1
0x0000_000C
Various hardware faults
SVCall
-
Can be set
0x0000_002C
System service called by SWI instruction
PendSV
-
Can be set
0x0000_0038
Pending system service
SysTick
-
Can be set
0x0000_003C
System tick timer
WWDT
0
Can be set
0x0000_0040
Window watchdog interrupt
-
1
-
0x0000_0044
Reserved
RTC
2
Can be set
0x0000_0048
RTC interrupt
