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Different wait cycles should be configured for different system clocks:
0 wait cycle: 0<system clock
≤
24MHz
1 wait cycle: 24MHz<system clock
≤
48MHz
Prefetch buffer
It can improve the reading speed and every time it is reset, the prefetch buffer
will be automatically opened; the read interface with prefetch buffer. It can be
configured only when the system clock is consistent with AHB clock and is less
than 24MHz, and can be used only when the system clock is consistent with
AHB clock.
Half-cycle access
When the power consumption needs to be optimized, half-cycle access can be
used; at this time, the system clock and AHB clock are consistent, and the
system clock is 8MHz or less than 8MHz, then half-cycle access to Flash can be
used, otherwise, it must be turned on.
Main Memory Block
3.4.2.1
Erase main memory block
FMC supports page erase and mass erase (full erase) to initialize the contents of
the main memory area to high level (the data is represented as 0xFFFF). Before
writing to Flash, users are advised to erase the write address page. If the data of
write address is not 0xFFFF, a programming error will be triggered.
Main memory page erase
Page erase is an independent erase according to the main memory area page
selected by the program, which will not have any impact on the page not
selected for erasure.
After the correct page erase (or flash write operation) is completed, OCF of
FMC_STS register will be set. If OCIE interrupt is enabled, an operation
completion interrupt will be triggered. Users need to note that the page to be
erased must be a valid page (the valid address of the main memory area and the
address not protected by write).
Main memory mass erase
The mass erase operation will erase all the contents in the main storage area of
Flash, and the mass erase operation will erase all the data in the main memory
area, so the users need to pay special attention when using it to avoid the loss of
important data caused by misoperation.
3.4.2.2
Write main memory block
FMC supports the writing of 16-bit (half word) data in the main memory area. You
can select Debug, BootLoader, program running in SRAM, and directly reading
the erased page to judge whether the erasing is successful.
In order to ensure correct writing, it is necessary to check whether the
destination address has been erased before writing; if it is not erased, the written
data will be invalid and PEF bit of FMC_STS register will be set to "1". If the
destination address has write protection, the written data is invalid and a write
protection error will be triggered (WPEF bit of FMC_STS is set to "1").
3.4.2.3
Main memory block of read/write protection
Read/Write protection of the flash is used to prevent illegal reading/modification
of the main memory area code or data, and it is controlled by the read/write
protection configuration byte of option byte. For APM32F030x4x6x8xC series
