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10.4
Functional Description
（
1
）
Realize the on-line programming and debugging of the chip
（
2
）
Using KEIL/IAR and other software to achieve on-line debugging,
downloading and programming
（
3
）
Flexible implementation of production of bus-line programmer
10.5
Register Address Mapping
Table 36 DBGMCU Register Address Mapping
Register name
Description
Offset address
DBGMCU_IDCODE
Debug MCU device ID register
0x4001 5800
DBGMCU_CFG
Debug MCU configuration register
0x4001 5804
DBGMCU_APB1F
Debug MCU APB1 freeze register
0x4001 5808
DBGMCU_APB2F
Debug MCU APB2 freeze register
0x4001 580C
10.6
Register Functional Description
Debug MCU device ID register (DBGMCU_IDCODE)
Address: 0x4001 5800
Only support 32-bit access
Reset value: 0xXXXX XXXX
Field Name R/W
Description
11:0
EQR
R
Equipment Recognition
This field indicates device ID
15:12
Reserved
31:16
WVR
R
Wafer Version Recognition
This field indicates the device version
Debug MCU configuration register (DBGMCU_CFG)
This register allows MCU to be configured during debugging and supports
low-power mode.
It is reset asynchronously by POR (not reset by system), and it can be written by
debugger through system reset.
If the debugging host does not support these characteristics, the user software
can write to these registers.
Only support 32-bit access
Address: 0x4001 5804
Reset value: 0x0000 (unaffected by system reset)
Field
Name
R/W
Description
0
Reserved
1
STOP_CLK_STS
R/W
Debug Stop Mode Configure
0: In the stop mode when both FCLK and HCLK are turned off, all
clocks will be disabled by clock controller. When exiting the
stop mode, the clock configuration is the same as that after
