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Field
Name
R/W
Description
0
ADDR1[0]
R/W
Master Address Setup
When the address mode is 7 bits, the bit is invalid; when the address
mode is 10 bits, this bit is the 0 bit of the address.
7:1
ADDR1[7:1]
R/W
Master Address Setup
The bit[7:1] of master address
9:8
ADDR1[9:8]
R/W
Master Address Setup
When the address mode is 7 bits, the bit is invalid; when the address
mode is 10 bits, this bit is the bit [9:8] of the address.
10
ADDR1LEN
R/W
Master Address Length Configure
0: 7-bit addressing mode
1: 10-bit addressing mode
14:11
Reserved
15
ADDR1EN
R/W
Master Address 1 Enable
0: Disable. Transfer NACK after the slave address ADDR is received
1: Enable. Transfer ACK after the slave address ADDR is received
31:16
Reserved
Master address register 2 (I2C_ADDR2)
Offset address: 0x0C
Reset value: 0x0000 0000
Field
Name
R/W
Description
0
Reserved
7:1
ADDR2[7:1]
R/W
Master Address Setup
Master address bit [7:1]
10:8
ADDR2MSK
R/W
Masks Master Address 2 Select
000: No mask
001: Mask ADDR2[1], compared with ADDR2[7:2].
010: Mask ADDR2[2:1], compared with ADDR2[7:3].
011: Mask ADDR2[3:1], compared with ADDR2[7:4].
100: Mask ADDR2[4:1], compared with ADDR2[7:5].
101: Mask ADDR2[5:1], compared with ADDR2[7:6].
110: Mask ADDR2[6:1], compared with ADDR2[7].
111: Mask ADDR2[7:1], without comparison; all 7-bit addresses
received will send ACK.
This bit can be set only when ADDR2EN bit is not set; if ADDR2MSK is
not 0, and the reserved I2C address does not response, matching is
meaningless.
14:11
Reserved
15
ADDR2EN
R/W
Master Address 2 Enable
0: Disable. Send NACK after the slave address ADDR2 is received.
1: Enable. Send ACK after receiving the slave address ADDR2.
31:16
Reserved
Timing register (I2C_TIMING)
Offset address: 0x10
