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Field
Name
R/W
Description
16
RTCRST
R/W
RTC Domain Software Reset
Set 1 or clear 0 by software
0: Reset is not activated
1: Reset RTC domain (only affecting LSECLK oscillator, RTC clock and
register RCM_RTCCTRL)
31:17
Reserved
Control/State register (RCM_CSTS)
Offset address: 0x24
Reset value: 0xXXX0 0000, except reset flag, all are cleared by system reset,
and reset flag can only be cleared by power reset.
Access: Access in the form of word, half word and byte, with 0 to three wait
cycles.
When the register is accessed continuously, the waiting state will be inserted.
Field
Name
R/W
Description
0
LSIEN
R/W
Low-Speed Internal Oscillator Enable
Set 1 or clear 0 by software.
0: Disable
1: Enable
1
LSIRDYFLG
R
Low-Speed Internal Oscillator Ready Flag
When LSICLK is stable, this bit is set to 1 by hardware, and
when it is unstable, it is cleared by hardware.
0: Not ready
1. Ready
22:2
Reserved
23
PWRRSTFLG
R
Reset Flag of The 1.5V Domain
It is set by software and cleared by setting RSTFLGCLR.
24
RSTFLGCLR
RT_W
Reset Flag Clear
The reset flag is set or cleared by software, including
RSTFLGCLR.
0: No effect
1: Clear the reset flag
25
OBRSTFLG
R
Option Byte Loader Reset Flag
When the option byte load reset occurs, it is set by hardware;
otherwise, it is set and cleared by RSTFLGCLR.
0: Reset does did not occur
1: Reset occurred
26
PINRSTFLG
R
PIN Reset Flag
It is set by hardware when pin reset occurs; otherwise it is
cleared by setting RSTFLGCLR.
0: Reset does did not occur
1: Reset occurred
27
PODRSTFLG
R
POR/PDR Reset Occur Flag
Set 1 by hardware; clear 0 by software by writing RSTFLGCLR
bit.
