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Table 84 External Trigger
Trigger source
EXTTRGSEL
Trigger type
TMR1_TRGO
000
Internal signal generated by on-chip timer
TMR1_CC4
001
TMR3_TRGO
010
TMR1_TRGO
011
TMR15_TRGO
100
Reserved
101
Reserved
110
Reserved
111
External pin
When the bit EXTPOLSEL
≠
"0b00" for the register ADC_CFG1, the external
event can trigger conversion on its selected polarity.
Table 85 Configuration Trigger Polarity
EXTPOLSEL
Source
00
Detection of disabled trigger
01
Detection on rising edge
10
Detection on falling edge
11
Detection on both rising edge and falling edge
Data Register
The data can be left-aligned or right-aligned, which is determined by DALIGCFG
bit of configuration register ADC_CFG1 ADC conversion results can be
left-aligned or right-aligned and stored in 16-bit data register.
Programmable Conversion Resolution
Reducing the resolution can improve the conversion time and 12, 10, 8 or 6-bit
modes can be selected by DATARESCFG bit of configuration register
ADC_CFG1.
Table 86 Conversion Time of tSAR Related to Conversion Resolution
DATARESCFG bit
t
SAR
t
SAR
(ns)@f
ADC
=14MHz
t
SMPL(min)
t
ADC
t
ADC
(μs)@f
ADC
=14MHz
6
7.5
535ns
1.5
9
643ns
8
9.5
678ns
1.5
11
785ns
10
11.5
821ns
1.5
13
928ns
12
12.5
893ns
1.5
14
1000ns
Interrupt
Table 87 ADC Interrupt
Interrupt event
Event flag
Enable control
End of conversion
EOCFLG
EOCIEN
