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Field
Name
R/W
Description
3
CCDSEL
R/W
Capture/compare DMA Select
0: Send DMA request of CCx when CCx event occurs
1: Send DMA request of CCx when an update event occurs
6:4
MMSEL
R/W
Master Mode Signal Select
The signals of timers working in master mode can be used for TRGO,
which affects the work of timers in slave mode and cascaded with master
timer, and specifically affects the configuration of timers in slave mode.
000: Reset; the reset signal of master mode timer is used for TRGO
001: Enable; the counter enable signal of master mode timer is used for
TRGO
010: Update; the update event of master mode timer is used for TRGO
011: Comparison pulses; when the master mode timer captures/compares
successfully (CCxIFLG=1), a pulse signal is output for TRGO
100: Comparison mode 1; OC1REF is used to trigger TRGO
101: Comparison mode 2; OC2REF is used to trigger TRGO
110: Comparison mode 3; OC3REF is used to trigger TRGO
111: Comparison mode 4; OC4REF is used to trigger TRGO
7
TI1SEL
R/W
Timer Input 1 Select
0: TMRx_CH1 pin is connected to TI1 input
1: TMRx_CH1, TMRx_CH2 and TMRx_CH3 pins are connected to TI1
input after exclusive
8
OC1OIS
R/W
OC1 Output Idle State Configure
Only the level state after the dead time of OC1 is affected when MOEN=0
and OC1N is realized.
0
：
OC1=0
1
：
OC1=1
Note: When LOCKCFG bit in TMRx_BDT register is at the Level 1, 2 or 3,
this bit cannot be modified.
9
OC1NOIS R/W
OC1N Output Idle State Configure
Only the level state after the dead time of OC1 is affected when MOEN=0
and OC1N is realized.
0
：
OC1N=0
1
：
OC1N=1
Note: When LOCKCFG bit in TMRx_BDT register is at the Level 1, 2 or 3,
this bit cannot be modified.
10
OC2OIS
R/W Configure OC2 output idle state. Refer to OC1OIS bit
11
OC2NOIS R/W Configure OC2N output idle state. Refer to OC1NOIS bit
12
OC3OIS
R/W Configure OC3 output idle state. Refer to OC1OIS bit
13
OC3NOIS R/W Configure OC3N output idle state. Refer to OC1NOIS bit
14
OC4OIS
R/W Configure OC4 output idle state. Refer to OC1OIS bit
15
Reserved
Slave mode control register (TMRx_SMCTRL)
Offset address: 0x08
Reset value: 0x0000
Field
Name
R/W
Description
2:0
SMFSEL
R/W
Slave Mode Function Select
000: Disable the slave mode, the timer can be used as master mode
timer to affect the work of slave mode timer; if
CTRL1_CNTEN=1, the prescaler is directly driven by the
internal clock.
001: Encoder mode 1; according to the level of TI1FP1, the counter
counts at the edge of TI2FP2.
010: Encoder mode 2; according to the level of TI2FP2, the counter
counts at the edge of TI1FP1.
