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Field
Name
R/W
Description
+7 of TMRx_CTRL1 means the address of the data to be
written/read,
Data transmission will occur to: TMRx_CTRL1 a seven registers
starting from DBADDR.
The data transmission will change according to different DMA data length:
(1)
When the transmission data is set to 16 bits, the data will be
transmitted to seven registers
(2)
When the transmission data is set to 8 bits, the data of the first
register is the MSB bit of the first data, the data of the second
register is the LSB bit of the first data, and the data will still be
transmitted to seven registers.
15:13
Reserved
DMA address register of continuous mode (TMRx_DMADDR)
Offset address: 0x4C
Reset value: 0x0000
Field
Name
R/W
Description
15:0
DMADDR R/W
DMA Register for Burst Transfer
Read or write operation access of TMRx_DMADDR register may lead to
access operation of the register in the following address:
TMRx_CTRL1 a (DMA index) ×4
Wherein:
"TMRx_CTRL1 address" is the address of control register 1
(TMRx_CTRL1);
"DBADDR" is the base address defined in TMRx_DCTRL register;
"DMA index" is the offset automatically controlled by DMA, and it depends
on DBLEN defined in TMRx_DCTRL register.
