www.geehy.com Page 319
Field
Name
R/W
Description
31
CAL
R/S
ADC Calibrate
This bit is set to 1 by software and cleared by hardware.
0: Calibration is completed
1: Start calibration
Note: CAL bit can be set by software only when ADC is disabled.
ADC configuration register 1 (ADC_CFG1)
Offset address: 0x0C
Reset value: 0x0000 0000
Field
Name
R/W
Description
0
DMAEN
R/W
DMA Enable
0: DMA is disabled
1: DMA is enabled
1
DMACFG
R/W
DMA Mode Configure
This bit is valid only when DMAEN=1.
0: DMA single mode
1: DMA circular mode
2
SCANSEQDIR
R/W
Scan Sequence Direction Configure
0: Scan forward (from CHSEL0 to CHSEL16)
1: Scan backward (from CHSEL16 to CHSEL0)
4:3
DATARESCFG
R/W
Data Resolution Configure
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
5
DALIGCFG
R/W
Data Alignment Configure
0: Right alignment
1: Left alignment
8:6
EXTTRGSEL
R/W
External Trigger Event Select
These bits are used to select the external event for triggering ADC
conversion.
000: Event 0
001: Event 1
010: Event 2
011: Event 3
100: Event 4
101: Event 5
110: Event 6
111: Event 7
9
Reserved
11:10
EXTPOLSEL
R/W
External Trigger Enable and Polarity Select
00: Hardware trigger detection is disabled (conversion can be started
by software)
01: Hardware trigger detected on rising edge
10: Hardware trigger detected on falling edge
11:: Hardware trigger detected on both rising and falling edges
12
OVRMAG
R/W
Overrun Management Mode
0: When an overrun event is detected, ADC_DATA register saves
previous data
1: When an overrun event is detected, ADC_DATA register saves the
last converted data
