Geehy SEMICONDUCTOR APM32F030x4x6x8xC, User Manual

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16.7
TMR16 and TMR17 Register Address Mapping
In the following table, all registers of TMR16 and TMR17 are mapped to a 16-bit
addressable (address) space.
Table 54 TMR16 and TMR17 Register Address Mapping
Register name Description Offset address
TMRx_CTRL1 Control register 1 0x00
TMRx_CTRL2 Control register 2 0x04
TMRx_DIEN DMA/Interrupt enable register 0x0C
TMRx_STS State register 0x10
TMRx_CEG Control event generation register 0x14
TMRx_CCM1 Capture/Compare mode register 0x18
TMRx_CCEN Capture/Compare enable register 0x20
TMRx_CNT Counter register 0x24
TMRx_PSC Prescaler register 0x28
TMRx_AUTORLD Auto reload register 0x2C
TMRx_REPCNT Repeat count register 0x30
TMRx_CC1 Channel 1 capture/compare register 0x34
TMRx_BDT Break and dead-time register 0x44
TMRx_DCTRL DMA control register 0x48
TMRx_DMADDR DMA address register of continuous mode 0x4C
16.8
TMR16 and TMR17 Register Functional Description
Control register 1 (TMRx_CTRL1)
Offset address: 0x00
Reset value: 0x0000
Field Name R/W Description
0 CNTEN R/W
Counter Enable
0: Disable
1: Enable
When the timer is configured as external clock, gated mode and encoder
mode, it is required to write 1 to the bit by software to start regular work; when
it is configured as the trigger mode, it can be written to 1 by hardware.
1 UD R/W
Update Disable
Update event can cause
AUTORLD, PSC and CCx to generate the value of
update setting .
0: Update event is allowed (UEV)
An update event can occur in any of the following situations:
The counter overruns/underruns;
Set UEG bit;