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Field
Name
R/W
Description
7
ERRIEN
R/W
Error Interrupt Enable
0: Disable
1: When the position 1 of any of the following state register is
enabled, the interrupt will be generated: SMBALTFLG, TTEFLG,
PECEFLG, OVRURFLG, ALFLG, and STS1_BERRFLG
11:8
DNFCFG
R/W
Digital Noise Filter Configure
The digital noise filters of SDA and SCL are configured by this bit field.
The length of digital filter is DNFCFG[3:0]*t
I2C_CLK
.
0000: Disable
0001: Enabled; one t
I2C_CLK
……
1111:Enabled; 15 t
I2C_CLK
If the analog filter is enabled at the same time, the digital filter will be
added to the analog filter;
This bit can be set only when I2CEN is not set.
12
ANFD
R/W
Analog Noise Filter Disable
0: Enable
1: Disable
This bit can be set only when I2CEN is not set.
13
Reserved
14
DMATXEN
R/W
DMA Transmit Enable
0: Disable
1: Enable
15
DMARXEN
R/W
DMA Receive Enable
0: Disable
1: Enable
16
SBCEN
R/W
Slave Byte Control Enable
0: Disable
1: Enable
17
CLKSTRETCHD R/W
Slave Mode Clock Stretching Disable
0: Enable
1: Disable
This bit can be set only when I2CEN is not set, and it is applicable
only to the slave mode.
18
Reserved
19
RBEN
R/W
Responds
Broadcast
Enable
The address of response to broadcast is 0x00.
0: Disable
1: Enable
20
HADDREN
R/W
SMBus Host Address Enable
The HOST address is 0x10/0x11.
0: Disable
1: Enable
If SMBus mode is not supported, this bit will be reserved and be
forced to 0.
21
DEADDREN
R/W
SMBus Device Default Address Enable
The default address is 0xC2/0xC3.
0: Disable
1: Enable
If SMBus mode is not supported, this bit will be reserved and be
forced to 0.
22
ALTEN
R/W
SMBus Alert Function Enable
Device mode (HADDREN=0):
0: Release SMBALERT pin and disable the notification response
address header after NACK.
1: Pull down SMBALERT pin and enable the notification response
address header after ACK.
HOST mode (HADDREN=1):
