Geehy SEMICONDUCTOR APM32F030x4x6x8xC, User Manual

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Register name Description Offset address
TMRx_PSC Prescaler register 0x28
TMRx_AUTORLD Auto reload register 0x2C
TMRx_CC1 Channel 1 capture/compare register 0x34
TMRx_CC2 Channel 2 capture/compare register 0x38
TMRx_CC3 Channel 3 capture/compare register 0x3C
TMRx_CC4 Channel 4 capture/compare register 0x40
TMRx_DCTRL DMA control register 0x48
TMRx_DMADDR DMA address register of continuous mode 0x4C
14.6
Register Functional Description
Control register 1 (TMRx_CTRL1)
Offset address: 0x00
Reset value: 0x0000
Field Name R/W Description
0 CNTEN R/W
Counter Enable
0: Disable
1: Enable
When the timer is configured as external clock, gated mode and encoder
mode, it is required to write 1 to the bit by software to start regular work; when
it is configured as the trigger mode, it can be written to 1 by hardware.
1 UD R/W
Update Disable
Update event can cause AUTORLD, PSC and CCx to generate the value of
update setting.
0: Update event is allowed (UEV)
An update event can occur in any of the following situations:
The counter overruns/underruns;
Set UEG bit;
Update generated by slave mode controller.
1: Update event is disabled
2 URSSEL R/W
Update Request Source Select
If interrupt or DMA is enabled, the update event can generate update
interrupt or DMA request. Different update request sources can be selected
through this bit.
0: The counter overruns or underruns
Set UEG bit
Update generated by slave mode controller
1: The counter overruns or underruns
3 SPMEN R/W
ingle Pulse Mode Enable
When an update event is generated, the output level of the channel can be
changed; in this mode, the CNTEN bit will be cleared, the counter will be
stopped, and the output level of the channel will not be changed.
0: Disable
1: Enable
4 CNTDIR R/W
Counter Direction
This bit is read-only when the counter is configured as center-aligned mode
or encoder mode.