www.geehy.com Page 284
Field
Name
R/W
Description
0: Not supported
1: Supported
If ALTEN=0, SMBALERT pin can be used as a GPIO;
If SMBus mode is not supported, this bit will be reserved and be
forced to 0.
23
PECEN
R/W
PEC Enable
0: Disable
1: Enable
If SMBus mode is not supported, this bit will be reserved and be
forced to 0.
31:24
Reserved
Control register 2 (I2C_CTRL2)
Offset address: 0x04
Reset value: 0x0000 0000
Field
Name
R/W
Description
0
SADDR[0]
R/W
Slave Address Setup
When the address mode is 7 bits, the bit is invalid; when the address
mode is 10 bits, this bit is The bit 0 of the address
.
7:1
SADDR[7:1]
R/W
Slave Address Setup
The bit [7:1] of slave address.
9:8
SADDR[9:8]
R/W
Slave Address Setup
When the address mode is 7 bits, the bit is invalid; when the address
mode is 10 bits, this bit is the 9:8 bit of the address.
10
TXDIR
R/W
Master Mode Transfer Direction Setup
0: Write transmission
1: Read transmission
11
SADDRLEN
R/W
Slave Address Length Configure
0: 7-bit addressing mode
1: 10-bit addressing mode
12
ADDR10
R/W
Master Transmit 10-Bit Address Header Configure
0: Transmit 10-bit slave address read sequence: start bit + 2-byte 10-bit
write direction a r the first 7 bits of 10-bit read direction
address.
1: Transmit the first 7 bits of 10-bit slave address read se read
direction.
13
START
R/W
Start Bit Transfer
This bit can be set to 1 and cleared by software; it can be cleared by
hardware after the start bit and address sequence are transmitted,
arbitration loss occurs, timeout error occurs or I2CEN bit is not set, or
be cleared by setting ADDRMCLR bit of I2C_INTFCLR register.
In master mode:
0: Not send
1: Transmit repeatedly
In slave mode:
0: Not send
1: Transmit when the bus is idle
It is meaningless to write 0 to this bit;
Setting RELOAD bit and this bit does not work.
14
STOP
R/W
Stop Bit Transfer
This bit can be set to 1 and cleared by software; it can be cleared by
hardware when transmitting the stop bit or when I2CEN bit is not set.
