AT32F425
Series Reference Manual
2022.03.30
Page 262
Ver 2.01
Figure 14-95
One-pulse mode
0
1
2
3
4
5
6
...
40
41
42
43
44
...
5F
60
61
0
COUNTER
61
PR[15
：
0]
42
C1DT[15
：
0]
TRGIN
C1ORAW
C1OUT
CxORAW clear
When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level
to the EXT input. The CxORAW signal remains unchanged until the next overflow event.
This function can only be used in output capture or PWM modes, and does not work in forced mode.
shows the example of clearing CxORAW. When the EXT input is high, the CxORAW signal,
which was originally high, is driven low; when the EXT is low, the CxORAW signal outputs the
corresponding level according to the comparison result between the counter value and CxDT value.
Figure 14-96
Clearing CxORAW(PWM mode A) by EXT input
0
1
2
3
4
5
6
7
8
9
A
B
C
D
0
1
2
3
COUNTER
CxOSEN
7
CxDT
EXT
CxORAW
Dead-time insertion
The channel 1 to 3 of the advanced-control timers contains a set of reverse channel output. This function
is enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to Table 14-17
for more information
about the output state of CxOUT and CxCOUT.
The dead-time is activated when switching to IDLEF state (OEN falling down to 0).
Setting both CxEN and CxCEN bits, and using DTC[7:0] bit to insert dead-time of different durations.
After the dead-time insertion, the rising edge of the CxOUT is delayed compared to the rising edge of
the reference signal; the rising edge of the CxCOU is delayed compared to the falling edge of the
reference signal.
If the delay is greater than the width of the active output, and if C1OUT and C1COUT are to generate
corresponding pulses, the dead-time should be less than the width of the active output.
gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and
CxCEN=1.
Figure 14-97
Complementary output with dead-time insertion
Delay
Delay
C1ORAW
C1OUT
C1COUT
