AT32F425
Series Reference Manual
2022.03.30
Page 194
Ver 2.01
Figure 14-14
Overflow event when PRBEN=1
0
1
2
3
...
21
22
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
32
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
22
Clear
Clear
Clear
Downcounting mode
In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down
to 0, and restarts from the value programmed, and generates a counter underflow event.
Figure 14-15
Counter timing diagram with internal clock divided by 4
TMR_CLK
CNT_CLK
COUNTER
OVFIF
0
1
2
3
4
DIV[15
：
0]
32
31
30
32
PR[15
：
0]
Clear
Up/down counting mode
In up/down counting mode, the counter counts up/down alternatively. When the counter counts from the
value programmed in the TMRx_PR register down to 1, an underflow event is generated, and then
restarts counting from 0; When the counter counts from 0 to the value of the TMRx_PR register -1, an
overflow event is generated, and then restarts counting from the value of the TMRx_PR register. The
OWCDIR bit indicates the current counting direction.
Note: The OWCDIR is ready-only in up/down counting mode.
Figure 14-16
Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32
0
1
2
3
...
31
32
31
30
2F
2E
...
2
1
0
1
2
3
COUNTER
31
32
31
30
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
32
Clear
Clear
Clear
11
TWCMSEL
[1
：
0]
Encoder interface mode
To enble the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two
inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down
on the edge of the other input. The OWCDIR bit indicates the direction of the counter, as shown in the
table below:
